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device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT 

Add NO_S0IX_SUPPORT for boards that do not support, or do not want
to support S0IX.

As all the boards in the tree that do this, don't support D3Cold,
add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is
selected to disable D3Cold support.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Sean Rhodes 2023-02-06 09:20:12 +00:00
parent e0e6bccd44
commit d6e04aa00b
11 changed files with 37 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/alderlake/Kconfig
View File

@ -326,12 +326,6 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 8
config SOC_INTEL_ALDERLAKE_S3
bool
default n
help
Select if using S3 instead of S0ix to disable D3Cold.
config ENABLE_SATA_TEST_MODE
bool "Enable test mode for SATA margining"
default n

4
src/soc/intel/alderlake/acpi/tcss.asl
View File

@ -583,7 +583,7 @@ Scope (\_SB.PCI0)
}
}
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
/*
* TCSS xHCI device

12
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@ -28,16 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x04)
#else
Return (0x03)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -49,12 +49,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -66,7 +66,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*

12
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
View File

@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*

8
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*
@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
/*
* XHCI controller _DSM method

2
src/soc/intel/alderlake/fsp_params.c
View File

@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
/* D3Hot and D3Cold for TCSS */
s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable;
s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
s_cfg->UsbTcPortEn = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {

6
src/soc/intel/tigerlake/Kconfig
View File

@ -205,12 +205,6 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 6
config SOC_INTEL_TIGERLAKE_S3
bool
default n
help
Select if using S3 instead of S0ix to disable D3Cold
config SOC_INTEL_UART_DEV_MAX
int
default 3

4
src/soc/intel/tigerlake/acpi/tcss.asl
View File

@ -676,7 +676,7 @@ Scope (\_SB.PCI0)
}
}
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@ -787,7 +787,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
/*
* TCSS xHCI device

12
src/soc/intel/tigerlake/acpi/tcss_dma.asl
View File

@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x04)
#else
Return (0x03)
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*
@ -40,7 +40,7 @@ Method (_S0W, 0x0)
*/
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -52,12 +52,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -69,7 +69,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*

12
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
View File

@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_ALDERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*

8
src/soc/intel/tigerlake/acpi/tcss_xhci.asl
View File

@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
}
/*
@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
#if CONFIG(D3COLD_SUPPORT)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#endif // SOC_INTEL_TIGERLAKE_S3
#endif // D3COLD_SUPPORT
/*
* XHCI controller _DSM method