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soc/amd/cezanne/romstage: Preload fspm.bin 

FSP-M is normally memmapped and then decompressed. The SPI DMA
controller can actually read faster than mmap. So by reading the
contents into a buffer and then decompressing we reduce boot time.

It is interesting that FSP-M takes an additional 8ms to execute. I
suspect since we call it 50ms earlier it's having to wait for one of
its dependencies.

BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
| 970 - loading FSP-M                                 | 0.316     | 0.997     Δ(  0.68,    0.05%) |
| 17 - starting LZ4 decompress (ignore for x86)       | 0.026     | 13.874    Δ( 13.85,    0.96%) |
| 18 - finished LZ4 decompress (ignore for x86)       | 64.361    | 0.337     Δ(-64.02,   -4.43%) |
| 2 - before RAM initialization                       | 0.534     | 0.529     Δ( -0.01,   -0.00%) |
| 950 - calling FspMemoryInit                         | 1.455     | 1.132     Δ( -0.32,   -0.02%) |
| 951 - returning from FspMemoryInit                  | 207.695   | 216.537   Δ(  8.84,    0.61%) |

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I850b1576501753a355e7b23745e04802a0560387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2021-11-10 13:14:32 -07:00 committed by Shelley Chen
parent a23ec07967
commit d6e0a90aa0
2 changed files with 4 additions and 4 deletions
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6
src/soc/amd/cezanne/fsp_s_params.c
View File

@ -18,10 +18,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
fsp_assign_vbios_upds(scfg);
/*
* At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
* before FSP-S was loaded, we would introduce contention onto the SPI bus and
* slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
* no SPI operations, we can read the APOB while FSP-S executes.
* At this point FSP-S has been loaded into RAM. Since FSP-S takes a while to execute
* and performs no SPI operations, we can read the APOB while FSP-S executes.
*/
start_apob_cache_read();
/*

2
src/soc/amd/cezanne/romstage.c
View File

@ -18,6 +18,8 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
preload_fspm();
fsp_memory_init(acpi_is_wakeup_s3());
/* Fixup settings FSP-M should not be changing */