soc/mediatek/mt8188: devapc: Add SCP domain setting
Configure the SCP to operate within domain 8, allowing it to access only the necessary registers. Any unauthorized access will be prevented by the DAPC. - Set SCP domain from domain 0 to domain 8. - Lock register settings down to prevent unexpected modification. BUG=b:270657858 TEST=scp bootup successful with dapc settings Change-Id: I049486c997542d91bd468e0f4662eafbca4c17e0 Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77883 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -1628,6 +1628,15 @@ static void dump_infra2_ao(uintptr_t base)
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base, read32(getreg(base, DOM_REMAP_0_0)));
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}
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static void dump_scp_master(uintptr_t base)
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{
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printk(BIOS_DEBUG, "[DEVAPC] SCP_DOM0:%#x SCP_DOM1:%#x SCP_DOM2:%#x Lock:%#x\n",
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read32(getreg(base, SCP_DOM0)),
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read32(getreg(base, SCP_DOM1)),
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read32(getreg(base, SCP_DOM2)),
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read32(getreg(base, ONETIME_LOCK)));
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}
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static void infra_init(uintptr_t base)
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{
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void *reg;
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@ -1745,6 +1754,27 @@ static void infra2_master_init(uintptr_t base)
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FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
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}
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static void scp_master_init(uintptr_t base)
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{
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SET32_BITFIELDS(getreg(base, SCP_DOM0),
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FOUR_BIT_DOM_REMAP_0, DOMAIN_8,
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FOUR_BIT_DOM_REMAP_2, DOMAIN_8,
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FOUR_BIT_DOM_REMAP_4, DOMAIN_8,
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FOUR_BIT_DOM_REMAP_6, DOMAIN_8);
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SET32_BITFIELDS(getreg(base, SCP_DOM1),
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FOUR_BIT_DOM_REMAP_0, DOMAIN_8,
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FOUR_BIT_DOM_REMAP_2, DOMAIN_8,
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FOUR_BIT_DOM_REMAP_4, DOMAIN_8,
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FOUR_BIT_DOM_REMAP_6, DOMAIN_8);
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SET32_BITFIELDS(getreg(base, SCP_DOM2),
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FOUR_BIT_DOM_REMAP_0, DOMAIN_8);
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/* Let SCP_DOM registers be read-only for security */
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write32(getreg(base, ONETIME_LOCK), 0x5);
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}
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const struct devapc_init_ops devapc_init[] = {
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{ DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc },
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{ DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc },
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@ -1752,6 +1782,7 @@ const struct devapc_init_ops devapc_init[] = {
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{ DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc },
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{ DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao },
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{ DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao },
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{ SCP_CFG_BASE, scp_master_init, dump_scp_master },
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};
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const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init);
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@ -58,6 +58,7 @@ enum {
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INFRA_TRACKER_BASE = IO_PHYS + 0x00314000,
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SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
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SSPM_CFG_BASE = IO_PHYS + 0x00440000,
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SCP_CFG_BASE = IO_PHYS + 0x00700000,
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SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000,
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DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000,
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DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000,
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@ -19,6 +19,13 @@ enum devapc_ao_offset {
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AO_APC_CON = 0x00F00,
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};
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enum scp_offset {
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SCP_DOM0 = 0xA0900,
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SCP_DOM1 = 0xA0904,
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SCP_DOM2 = 0xA0908,
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ONETIME_LOCK = 0xA5104,
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};
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/******************************************************************************
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* STRUCTURE DEFINITION
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******************************************************************************/
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