- Fix some copy bugs and thinkos in the i440bx SMbus
read code. SBbus reads to RAM now work. Yah! - Rename the register constants to something I can look at more easily. - Make the logic flow match the flow from V1 assembly - #if 0 out other SMbus functions that are still broken. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Richard Smith
parent
01789b630f
commit
d7088c459c
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@ -83,7 +83,7 @@ static void enable_shadow_ram(void)
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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unsigned char c;
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int c;
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c = smbus_read_byte(device, address);
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return c;
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}
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@ -100,11 +100,13 @@ static void main(unsigned long bist)
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.channel0 = {
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(0xa << 3) | 0,
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(0xa << 3) | 1,
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(0xa << 3) | 2, (0xa << 3) | 3,
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(0xa << 3) | 2,
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(0xa << 3) | 3,
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},
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}
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};
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unsigned long x;
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int result;
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if (bist == 0) {
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early_mtrr_init();
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@ -117,6 +119,12 @@ static void main(unsigned long bist)
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report_bist_failure(bist);
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enable_smbus();
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/*
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result = spd_read_byte(cpu[0].channel0[0],0x03);
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print_debug("Result: ");
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print_debug_hex16(result);
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print_debug("\r\n");
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*/
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dump_spd_registers(&cpu[0]);
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#if 0
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@ -11,7 +11,7 @@ static void enable_smbus(void)
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}
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uint8_t enable;
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print_spew("SMBus controller enabled\r\n");
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pci_write_config32(dev, 0x90, SMBUS_IO_BASE );
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pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1 );
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// Enable and set SMBBus
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// 0x01 Interrupt to SMI#
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// (0x4<<1)|1 set interrupt to IRQ9
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@ -21,7 +21,24 @@ static void enable_smbus(void)
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pci_write_config16(dev, 0x04, 1);
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/* clear any lingering errors, so the transaction will run */
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outb(0x1e, SMBUS_IO_BASE + SMBGSTATUS);
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outb(0x1e, SMBUS_IO_BASE + SMBHST_STATUS);
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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// The following functions are broken. Do no use until you
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// have fixed the low level code to do the right thing.
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//
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#if 0
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static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
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{
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return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
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}
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static int smbus_recv_byte(unsigned device)
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@ -33,13 +50,4 @@ static int smbus_send_byte(unsigned device, unsigned char val)
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{
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return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
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{
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return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
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}
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#endif
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@ -1,13 +1,14 @@
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#include <device/smbus_def.h>
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#define SMBGSTATUS 0x0
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#define SMBGCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBHSTADDR 0x4
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#define SMBHSTDAT 0x5
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#define SMBHST_STATUS 0x0
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#define SMBHST_CTL 0x2
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#define SMBHST_CMD 0x3
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#define SMBHST_ADDR 0x4
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#define SMBHST_DAT 0x5
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#define SMBUS_TIMEOUT (100*1000*10)
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#define SMBUS_STATUS_MASK 0x1e
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#define SMBUS_ERROR_FLAG (1<<2)
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static inline void smbus_delay(void)
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{
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@ -26,14 +27,16 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
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do {
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unsigned char val;
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smbus_delay();
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val = inb(smbus_io_base + SMBGSTATUS);
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val = inb(smbus_io_base + SMBHST_STATUS);
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if ((val & 0x1) == 0) {
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break;
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}
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#if 0
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if(loops == (SMBUS_TIMEOUT / 2)) {
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outw(inw(smbus_io_base + SMBGSTATUS),
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smbus_io_base + SMBGSTATUS);
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outw(inw(smbus_io_base + SMBHST_STATUS),
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smbus_io_base + SMBHST_STATUS);
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}
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#endif
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} while(--loops);
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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@ -46,7 +49,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
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unsigned short val;
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smbus_delay();
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val = inb(smbus_io_base + SMBGSTATUS);
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val = inb(smbus_io_base + SMBHST_STATUS);
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// Make sure the command is done
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if ((val & 0x1) != 0) {
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continue;
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@ -71,23 +74,23 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
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outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
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outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR);
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/* set the command/address... */
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outb(0, smbus_io_base + SMBHSTCMD);
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outb(0, smbus_io_base + SMBHST_CMD);
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/* set up for a send byte */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
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outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS);
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/* set the data word...*/
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outw(0, smbus_io_base + SMBHSTDAT);
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outw(0, smbus_io_base + SMBHST_DAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL);
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/* poll for transaction completion */
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@ -95,10 +98,10 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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global_status_register = inw(smbus_io_base + SMBHST_STATUS);
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTDAT) & 0xff;
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byte = inb(smbus_io_base + SMBHST_DAT) & 0xff;
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// Check for any result other than a command completion
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if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) {
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@ -117,30 +120,30 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
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outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
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outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR);
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/* set the command/address... */
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outb(0, smbus_io_base + SMBHSTCMD);
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outb(0, smbus_io_base + SMBHST_CMD);
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/* set up for a send byte */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
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outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS);
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/* set the data word...*/
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outw(value, smbus_io_base + SMBHSTDAT);
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outw(value, smbus_io_base + SMBHST_DAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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global_status_register = inw(smbus_io_base + SMBHST_STATUS);
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if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
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return SMBUS_ERROR;
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@ -151,7 +154,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
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static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
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{
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unsigned global_status_register;
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unsigned status_register;
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unsigned byte;
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if (smbus_wait_until_ready(smbus_io_base) < 0) {
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@ -161,30 +164,36 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
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/* setup transaction */
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/* clear any lingering errors, so the transaction will run */
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outb(0x1e, smbus_io_base + SMBGSTATUS);
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outb(0x1e, smbus_io_base + SMBHST_STATUS);
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
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outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR);
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/* set the command/address... */
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outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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outb(address & 0xff, smbus_io_base + SMBHST_CMD);
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/* clear the data word...*/
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outb(0, smbus_io_base + SMBHSTDAT);
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outb(0, smbus_io_base + SMBHST_DAT);
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/* start a byte read with interrupts disabled */
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outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBGCTL);
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outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBHST_CTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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status_register = inw(smbus_io_base + SMBHST_STATUS);
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/* read results of transaction */
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byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
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byte = inw(smbus_io_base + SMBHST_DAT) & 0xff;
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if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
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if (status_register & 0x04) {
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#if 0
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print_debug("Read fail ");
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print_debug_hex16(status_register);
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print_debug("\r\n");
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#endif
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return SMBUS_ERROR;
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}
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return byte;
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@ -200,29 +209,29 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned
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/* setup transaction */
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/* disable interrupts */
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outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
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outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
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outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR);
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outb(address & 0xFF, smbus_io_base + SMBHST_CMD);
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/* set up for a byte data write */ /* FIXME */
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outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
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outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x2), smbus_io_base + SMBHST_CTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
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outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS);
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/* write the data word...*/
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outw(val, smbus_io_base + SMBHSTDAT);
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outw(val, smbus_io_base + SMBHST_DAT);
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/* start the command */
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outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
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outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done(smbus_io_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inw(smbus_io_base + SMBGSTATUS);
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global_status_register = inw(smbus_io_base + SMBHST_STATUS);
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if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
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if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) {
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return SMBUS_ERROR;
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}
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return 0;
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