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nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use 

Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-09-27 07:24:17 +03:00
parent 197a3c6cea
commit d7205bebd5
6 changed files with 7 additions and 20 deletions
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2
src/northbridge/intel/fsp_rangeley/northbridge.h
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@ -63,9 +63,7 @@ void rangeley_late_initialization(void);
u32 sideband_read(int port, int reg);
void sideband_write(int port, int reg, long data);
#ifndef __SIMPLE_DEVICE__
void northbridge_acpi_fill_ssdt_generator(struct device *device);
#endif
#endif /* #ifndef __ASSEMBLER__ */
#endif /* #ifndef __ACPI__ */

2
src/northbridge/intel/gm45/gm45.h
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@ -449,12 +449,10 @@ int get_blc_values(const struct blc_pwm_t **entries);
u16 get_blc_pwm_freq_value(const char *edid_ascii_string);
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp);
#endif
#endif /* !__ACPI__ */
#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */

6
src/northbridge/intel/haswell/haswell.h
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@ -208,24 +208,20 @@
#ifndef __ASSEMBLER__
static inline void barrier(void) { asm("" ::: "memory"); }
#ifdef __SMM__
void intel_northbridge_haswell_finalize_smm(void);
#else /* !__SMM__ */
void haswell_early_initialization(int chipset_type);
void haswell_late_initialization(void);
void set_translation_table(int start, int end, u64 base, int inc);
void haswell_unhide_peg(void);
void report_platform_info(void);
#endif /* !__SMM__ */
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(struct device *device,
unsigned long start, struct acpi_rsdp *rsdp);
#endif
#endif
#endif

2
src/northbridge/intel/sandybridge/sandybridge.h
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@ -227,12 +227,10 @@ int mainboard_should_reset_usb(int s3resume);
void perform_raminit(int s3resume);
enum platform_type get_platform_type(void);
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp);
#endif
#endif
#endif

6
src/northbridge/intel/x4x/x4x.h
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@ -368,7 +368,6 @@ enum ddr2_signals {
CTRL3,
};
#ifndef __BOOTBLOCK__
void x4x_early_init(void);
void x4x_late_init(int s3resume);
u32 decode_igd_memory_size(u32 gms);
@ -411,10 +410,9 @@ extern const u32 ddr3_c2_tab[2][3][6][2];
extern const u8 ddr3_c2_x264[3][6];
extern const u16 ddr3_c2_x23c[3][6];
#include <device/device.h>
struct acpi_rsdp;
#ifndef __SIMPLE_DEVICE__
unsigned long northbridge_write_acpi_tables(struct device *device,
unsigned long start, struct acpi_rsdp *rsdp);
#endif /* __SIMPLE_DEVICE__ */
#endif
#endif /* __NORTHBRIDGE_INTEL_X4X_H__ */

9
src/southbridge/intel/i82801dx/i82801dx.h
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@ -30,14 +30,13 @@
#include <arch/acpi.h>
#if !defined(__ASSEMBLER__)
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#include "chip.h"
extern void i82801dx_enable(struct device *dev);
#else
void i82801dx_enable(struct device *dev);
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
#endif
void aseg_smm_lock(void);
#endif