mb/google/brya/var/felwinter: Correct typeC EC mux port

Type C port2 uses EC mux port0 as per schematics.

BUG=b:204230406
TEST=No error message in depthahrge.
update_port_state: port C2: get_usb_pd_mux_info failed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/variants/felwinter/overridetree.cb

@@ -123,10 +123,9 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pch_espi on
-			#TBD, felwinter remove typeC port0
 			chip ec/google/chromeec
 				use conn1 as mux_conn[1]
-				use conn2 as mux_conn[2]
+				use conn2 as mux_conn[0]
 				device pnp 0c09.0 on end
 			end
 		end