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util/inteltool: Add chip detection for IceLake chips 

Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johanna Schander 2019-12-29 14:31:01 +01:00 committed by Philipp Deppenwiese
parent 8fa02a8ef9
commit d756c27a54
2 changed files with 9 additions and 0 deletions
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6
util/inteltool/inteltool.c
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@ -139,6 +139,8 @@ static const struct {
"7th generation (Kaby Lake family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3,
"7th generation (Kaby Lake family) Core Processor Xeon E3-1200" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U,
"10th generation (Icelake family) Core Processor (Mobile)" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
@ -216,6 +218,8 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_U,
"Icelake U LPC" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL,
"Lynx Point Low Power Full Featured Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM,
@ -433,6 +437,8 @@ static const struct {
"Intel(R) Iris Plus Graphics 650" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_655,
"Intel(R) Iris Plus Graphics 655" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7,
"Intel(R) Iris Plus Graphics G7" },
};
#ifndef __DARWIN__

3
util/inteltool/inteltool.h
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@ -106,6 +106,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_3450 0x3b16
#define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_U 0x3482
#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
#define PCI_DEVICE_ID_INTEL_P67 0x1c46
#define PCI_DEVICE_ID_INTEL_UM67 0x1c47
@ -291,6 +292,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */
#define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */
/* Intel GPUs */
@ -359,6 +361,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_IRIS_PRO_580 0x193B
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_650 0x5927
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
#if !defined(__DARWIN__) && !defined(__FreeBSD__)
typedef struct { uint32_t hi, lo; } msr_t;