mb/dell/snb_ivb_workst: Remove superfluous comments about PCI devices

Since all devicetrees from dell/snb_ivb_workstation are using the
reference names for PCI devices now, remove the equivalent comments
documenting their function.

Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Felix Singer 2024-01-18 06:53:02 +01:00 committed by Felix Singer
parent 8c9c7f5070
commit d759f96587
3 changed files with 37 additions and 37 deletions

View File

@ -7,12 +7,12 @@ chip northbridge/intel/sandybridge
end end
device domain 0 on device domain 0 on
device ref host_bridge on end # Host bridge Host bridge device ref host_bridge on end
device ref peg10 on # PEG1 (blue slot1) device ref peg10 on # blue slot1
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X" smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X"
end end
device ref igd on end # Internal graphics VGA controller device ref igd on end
device ref peg60 off end # PEG2 device ref peg60 off end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "gpe0_en" = "0x00002a46" register "gpe0_en" = "0x00002a46"
@ -30,25 +30,25 @@ chip northbridge/intel/sandybridge
register "superspeed_capable_ports" = "0x0000000f" register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x08040201" register "xhci_overcurrent_mapping" = "0x08040201"
register "xhci_switchable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end # USB 3.0 Controller device ref xhci on end
device ref mei1 off end # Management Engine Interface 1 device ref mei1 off end
device ref mei2 off end # Management Engine Interface 2 device ref mei2 off end
device ref me_ide_r off end # Management Engine IDE-R device ref me_ide_r off end
device ref me_kt off end # Management Engine KT device ref me_kt off end
device ref gbe on end # Intel Gigabit Ethernet device ref gbe on end
device ref ehci2 on end # USB2 EHCI #2 device ref ehci2 on end
device ref hda on end # High Definition Audio controller device ref hda on end
device ref pcie_rp1 off end # PCIe Port #1 device ref pcie_rp1 off end
device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp2 off end
device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp3 off end
device ref pcie_rp4 off end # PCIe Port #4 device ref pcie_rp4 off end
device ref pcie_rp5 off end # PCIe Port #5 device ref pcie_rp5 off end
device ref pcie_rp6 off end # PCIe Port #6 device ref pcie_rp6 off end
device ref pcie_rp7 off end # PCIe Port #7 device ref pcie_rp7 off end
device ref pcie_rp8 off end # PCIe Port #8 device ref pcie_rp8 off end
device ref ehci1 on end # USB2 EHCI #1 device ref ehci1 on end
device ref pci_bridge off end # PCI bridge device ref pci_bridge off end
device ref lpc on # LPC bridge device ref lpc on
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
@ -78,10 +78,10 @@ chip northbridge/intel/sandybridge
device pnp 2e.11 off end # PP device pnp 2e.11 off end # PP
end end
end end
device ref sata1 on end # SATA Controller 1 device ref sata1 on end
device ref smbus on end # SMBus device ref smbus on end
device ref sata2 off end # SATA Controller 2 device ref sata2 off end
device ref thermal on end # Thermal device ref thermal on end
end end
end end
end end

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@ -3,12 +3,12 @@ chip northbridge/intel/sandybridge
subsystemid 0x1028 0x052c inherit subsystemid 0x1028 0x052c inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0x7" register "sata_port_map" = "0x7"
device ref pcie_rp5 on # PCIe Port #5 device ref pcie_rp5 on
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
end end
device ref pcie_rp6 on end # PCIe Port #6 device ref pcie_rp6 on end
device ref pcie_rp7 on end # PCIe Port #7 device ref pcie_rp7 on end
device ref pcie_rp8 on end # PCIe Port #8 device ref pcie_rp8 on end
end end
end end
end end

View File

@ -4,16 +4,16 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0xf" register "sata_port_map" = "0xf"
device ref pcie_rp3 on # PCIe Port #3 device ref pcie_rp3 on
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X" smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
end end
device ref pcie_rp5 on # PCIe Port #5 device ref pcie_rp5 on
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X" smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
end end
device ref pcie_rp6 on end # PCIe Port #6 device ref pcie_rp6 on end
device ref pcie_rp7 on end # PCIe Port #7 device ref pcie_rp7 on end
device ref pcie_rp8 on end # PCIe Port #8 device ref pcie_rp8 on end
device ref pci_bridge on # PCI bridge device ref pci_bridge on
smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit" smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit"
end end
end end