soc/intel/quark: Disable the ROM shadow

Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing successful display of 0x000ffff0 - 0x000fffff does not match
   the end of the SPI flash.

Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/include/soc/QuarkNcSocId.h

@@ -269,6 +269,8 @@ Definitions beginning with "N_" are the bit position
 //
 #define QNC_MSG_FSBIC_REG_HMISC                0x03       // Host Misellaneous Controls
 #define   SMI_EN                              (BIT19)     // SMI Global Enable (from Legacy Bridge)
+#define   FSEG_RD_DRAM                        (BIT2)      // Enable RAM for 0x000f0000 - 0x000fffff
+#define   ESEG_RD_DRAM                        (BIT1)      // Enable RAM for 0x000e0000 - 0x000effff
 #define QNC_MSG_FSBIC_REG_HSMMC                0x04       // Host SMM Control
 #define   NON_HOST_SMM_WR_OPEN                (BIT18)     // SMM Writes OPEN
 #define   NON_HOST_SMM_RD_OPEN                (BIT17)     // SMM Writes OPEN

src/soc/intel/quark/include/soc/romstage.h

@@ -30,6 +30,8 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
 uint32_t mdr_read(void);
 void mdr_write(uint32_t value);
 void mea_write(uint32_t reg_address);
+uint32_t port_reg_read(uint8_t port, uint32_t offset);
+void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
 void report_platform_info(void);
 int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
 

src/soc/intel/quark/romstage/mtrr.c

@@ -73,6 +73,23 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
 	return offset;
 }
 
+uint32_t port_reg_read(uint8_t port, uint32_t offset)
+{
+	/* Read the port register */
+	offset = QNC_MSG_FSBIC_REG_HMISC;
+	mea_write(offset);
+	mcr_write(QUARK_OPCODE_READ, port, offset);
+	return mdr_read();
+}
+
+void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
+{
+	/* Write the port register */
+	mea_write(offset);
+	mdr_write(value);
+	mcr_write(QUARK_OPCODE_WRITE, port, offset);
+}
+
 msr_t soc_mtrr_read(unsigned long index)
 {
 	uint32_t offset;
@@ -83,18 +100,14 @@ msr_t soc_mtrr_read(unsigned long index)
 
 	/* Read the low 32-bits of the register */
 	offset = mtrr_index_to_host_bridge_register_offset(index);
-	mea_write(offset);
+	value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
-	mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
-	value.u64 = mdr_read();
 
 	/* For 64-bit registers, read the upper 32-bits */
 	if ((offset >=  QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
 		&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
 		offset += 1;
-		mea_write(offset);
+		value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
-		mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
 					   offset);
-		value.u64 |= mdr_read();
 	}
 	return value.msr;
 }
@@ -110,18 +123,14 @@ void soc_mtrr_write(unsigned long index, msr_t msr)
 	/* Write the low 32-bits of the register */
 	value.msr = msr;
 	offset = mtrr_index_to_host_bridge_register_offset(index);
-	mea_write(offset);
+	port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]);
-	mdr_write(value.u32[0]);
-	mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
 
 	/* For 64-bit registers, write the upper 32-bits */
 	if ((offset >=  QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
 		&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
 		offset += 1;
-		mea_write(offset);
+		port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset,
-		mdr_write(value.u32[1]);
+				value.u32[1]);
-		mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
-			offset);
 	}
 }
 

src/soc/intel/quark/romstage/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
+#include <lib.h>
 #include <soc/intel/common/util.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -86,6 +87,30 @@ void soc_memory_init_params(struct romstage_params *params,
 		config->PcdSmmTsegSize : 0;
 	upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file;
 	upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len;
+
+	/* Display the ROM shadow data */
+	hexdump((void *)0x000ffff0, 0x10);
+}
+
+void soc_after_ram_init(struct romstage_params *params)
+{
+	uint32_t data;
+
+	/* Determine if the shadow ROM is enabled */
+	data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
+				QNC_MSG_FSBIC_REG_HMISC);
+	printk(BIOS_DEBUG, "0x%08x: HMISC\n", data);
+	if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM))
+		!= (ESEG_RD_DRAM | FSEG_RD_DRAM)) {
+
+		/* Disable the ROM shadow 0x000e0000 - 0x000fffff */
+		data |= ESEG_RD_DRAM | FSEG_RD_DRAM;
+		port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
+			QNC_MSG_FSBIC_REG_HMISC, data);
+	}
+
+	/* Display the DRAM data */
+	hexdump((void *)0x000ffff0, 0x10);
 }
 
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,