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soc/amd/picasso/acpi: Change PCI0 BAR window 

Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Raul E Rangel 2021-02-18 16:50:47 -07:00 committed by Patrick Georgi
parent 0b123dd72e
commit d75ee46d3c
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/picasso/acpi/sb_pci0_fch.asl
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@ -73,9 +73,9 @@ Method(_CRS, 0) {
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
/* Declare memory between TOM1 and IOAPIC as available for PCI MMIO. */
/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
MM1B = TOM1
Local0 = IO_APIC_ADDR /* This is the first MMIO device after TOM1. */
Local0 = CONFIG_MMCONF_BASE_ADDRESS
Local0 -= TOM1
MM1L = Local0