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src/northbridge/amd: Remove unused variables 

Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2019-04-23 22:10:41 +02:00 committed by Patrick Georgi
parent 73b0136fa3
commit d768e919ae
3 changed files with 5 additions and 18 deletions
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12
src/northbridge/amd/amdmct/mct/mct_d.c
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@ -523,7 +523,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
{
u8 Node;
u32 NextBase, BottomIO;
u8 _MemHoleRemap, DramHoleBase, DramHoleOffset;
u8 _MemHoleRemap, DramHoleBase;
u32 HoleSize, DramSelBaseAddr;
u32 val;
@ -583,7 +583,6 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO))
base = DramSelBaseAddr;
val = ((base + HoleSize) >> (24-8)) & 0xFF;
DramHoleOffset = val;
val <<= 8; /* shl 16, rol 24 */
val |= DramHoleBase << 24;
val |= 1 << DramHoleValid;
@ -972,7 +971,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
u8 Twr, Trtp;
u8 Trp, Trrd, Trcd, Tras, Trc, Trfc[4], Rows;
u32 DramTimingLo, DramTimingHi;
u16 Tk10, Tk40;
u16 Tk40;
u8 Twtr;
u8 LDIMM;
u8 DDR2_1066;
@ -1095,7 +1094,6 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
if (byte == 5)
DDR2_1066 = 1;
Tk40 = Get_40Tk_D(byte);
Tk10 = Tk40 >> 2;
/* Notes:
1. All secondary time values given in SPDs are in binary with units of ns.
@ -1740,7 +1738,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
* and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3).
*/
u8 ChipSel, Rows, Cols, Ranks, Banks, DevWidth;
u8 ChipSel, Rows, Cols, Ranks, Banks;
u32 BankAddrReg, csMask;
u32 val;
@ -1773,7 +1771,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
Banks = mctRead_SPD(smbaddr, SPD_LBANKS);
byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH);
DevWidth = byte & 0x7f; /* bits 0-6 = bank 0 width */
byte = mctRead_SPD(smbaddr, SPD_DMBANKS);
Ranks = (byte & 7) + 1;
@ -1933,7 +1930,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
u8 b = 0;
u32 nxtcsBase, curcsBase;
u8 p, q;
u32 Sizeq, BiggestBank;
u32 BiggestBank;
u8 _DSpareEn;
u16 word;
@ -1989,7 +1986,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
val >>= 19;
val++;
val <<= 19;
Sizeq = val; //never used
if (val > BiggestBank) {
/*Bingo! possibly Map this chip-select next! */
BiggestBank = val;

7
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -5164,9 +5164,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
/* Special Jedec SPD diagnostic bit - "enable all clocks" */
if (!(pDCTstat->Status & (1<<SB_DiagClks))) {
const u8 *p;
const u32 *q;
p = Tab_ManualCLKDis;
q = (u32 *)p;
byte = mctGet_NVbits(NV_PACK_TYPE);
if (byte == PT_L1)
@ -5418,7 +5416,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
u8 b = 0;
u32 nxtcsBase, curcsBase;
u8 p, q;
u32 Sizeq, BiggestBank;
u32 BiggestBank;
u8 _DSpareEn;
u16 word;
@ -5471,7 +5469,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
val >>= 19;
val++;
val <<= 19;
Sizeq = val; /* never used */
if (val > BiggestBank) {
/*Bingo! possibly Map this chip-select next! */
BiggestBank = val;
@ -6983,7 +6980,6 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
u32 index_reg = 0x98;
u8 cs;
u8 odt;
u8 max_dimms;
dev = pDCTstat->dev_dct;
@ -6993,7 +6989,6 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
/* FIXME: skip for Ax */
/* Tri-state unused ODTs when motherboard termination is available */
max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
odt = 0x0f; /* ODT tri-state setting */
if (pDCTstat->Status & (1 <<SB_Registered)) {

4
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -684,11 +684,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
acpi_header_t *ssdt;
acpi_header_t *alib;
acpi_ivrs_t *ivrs;
acpi_hest_t *hest;
/* HEST */
current = ALIGN(current, 8);
hest = (acpi_hest_t *)current;
acpi_write_hest((void *)current, acpi_fill_hest);
acpi_add_table(rsdp, (void *)current);
current += ((acpi_header_t *)current)->length;
@ -910,7 +908,6 @@ static void domain_set_resources(struct device *dev)
struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info mem_hole;
u32 reset_memhole = 1;
#endif
pci_tolm = 0xffffffffUL;
@ -941,7 +938,6 @@ static void domain_set_resources(struct device *dev)
// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
mmio_basek = mem_hole.hole_startk;
reset_memhole = 0;
}
#endif