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mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors 

pcie_rst isn't working correctly, so use the AUX resets to reset the
PCIe devices before training.

BUG=b:182202136
TEST=See PCIe devices train & enumerate

Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Martin Roth 2021-04-05 17:24:51 -06:00 committed by Felix Held
parent fdf2fb78b5
commit d76b4f6607
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/guybrush/port_descriptors.c
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/platform_descriptors.h>
#include <soc/gpio.h>
#include <types.h>
/* TODO: test if this really works */
@ -14,6 +15,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.function_number = 1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.gpio_group_id = GPIO_29,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* SD */
@ -25,6 +27,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.function_number = 2,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ1,
.gpio_group_id = GPIO_70,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* WWAN */
@ -36,6 +39,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.function_number = 3,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ2,
.gpio_group_id = GPIO_18,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* NVME */
@ -47,6 +51,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.function_number = 4,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
.gpio_group_id = GPIO_40,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
}
};