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Some more DIMM0 related cleanups and deduplication. 

- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-20 20:23:08 +00:00
parent 9bd9a90d6a
commit d773fd370a
56 changed files with 250 additions and 1511 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
src/include/spd.h
View File

@ -166,5 +166,70 @@
#define DIMM6 0x56
#define DIMM7 0x57
#endif /* _SPD_H_ */
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#endif

5
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
//#include "spd_addr.h"
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

194
src/mainboard/amd/mahogany_fam10/spd_addr.h
View File

@ -1,194 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

83
src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h
View File

@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
@ -191,4 +113,3 @@ static const u8 spd_addr[] = {
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

5
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
//#include "spd_addr.h"
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

194
src/mainboard/amd/tilapia_fam10/spd_addr.h
View File

@ -1,194 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

5
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -86,11 +86,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
//#include "spd_addr.h"
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

194
src/mainboard/asus/m4a785-m/spd_addr.h
View File

@ -1,194 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

2
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -75,7 +75,7 @@ static const struct mem_controller ctrl = {
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { 0x50 },
.channel0 = { DIMM0 },
};
void main(unsigned long bist)

18
src/mainboard/dell/s1850/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -208,8 +206,8 @@ static void dump_pci_devices(void)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -233,7 +231,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -241,8 +239,8 @@ void dump_spd_registers(void)
void show_dram_slots(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -257,7 +255,7 @@ void show_dram_slots(void)
}
print_debug_hex8(status);
print_debug("\n");
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -285,7 +283,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

4
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -82,10 +82,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

4
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -86,10 +86,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

83
src/mainboard/hp/dl165_g6_fam10/spd_addr.h
View File

@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
// switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
@ -108,4 +30,3 @@ static const u8 spd_addr[] = {
RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

5
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -89,11 +89,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
//#include "spd_addr.h"
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

194
src/mainboard/iei/kino-780am2-fam10/spd_addr.h
View File

@ -1,194 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};

12
src/mainboard/intel/eagleheights/debug.c
View File

@ -20,9 +20,7 @@
* MA 02110-1301 USA
*/
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -230,8 +228,8 @@ static inline void dump_pci_devices(void)
static inline void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -254,7 +252,7 @@ static inline void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -281,7 +279,7 @@ static inline void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

12
src/mainboard/intel/jarrell/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

2
src/mainboard/jetway/j7f24/romstage.c
View File

@ -81,7 +81,7 @@ static const struct mem_controller ctrl = {
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { 0x50 },
.channel0 = { DIMM0 },
};
void main(unsigned long bist)

3
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -94,9 +94,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
#define RC00 0
#define RC01 1
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{

83
src/mainboard/msi/ms9652_fam10/spd_addr.h
View File

@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
@ -107,4 +29,3 @@ static const u8 spd_addr[] = {
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};

4
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -89,7 +89,7 @@ static u8 spd_read_byte(u8 device, u8 address)
print_debug("spd_read_byte dev ");
print_debug_hex8(device);
if (device != (0x50 << 1)) {
if (device != DIMM0) {
print_debug(" returns 0xff\n");
return 0xff;
}
@ -123,7 +123,7 @@ static void mb_gpio_init(void)
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {0x50}},
{.channel0 = {DIMM0}},
};
post_code(0x01);

4
src/mainboard/pcengines/alix2d/romstage.c
View File

@ -88,7 +88,7 @@ static u8 spd_read_byte(u8 device, u8 address)
print_debug("spd_read_byte dev ");
print_debug_hex8(device);
if (device != (0x50 << 1)) {
if (device != DIMM0) {
print_debug(" returns 0xff\n");
return 0xff;
}
@ -144,7 +144,7 @@ static void mb_gpio_init(void)
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {0x50}},
{.channel0 = {DIMM0}},
};
post_code(0x01);

7
src/mainboard/rca/rm4100/romstage.c
View File

@ -45,15 +45,16 @@
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
* socket0 (0x50), and the onboard memory is located in socket1 (0x51).
* socket0 (0x50/DIMM0), and the onboard memory is located in socket1
* (0x51/DIMM1).
*/
static inline int spd_read_byte(unsigned device, unsigned address)
{
int i;
if (device == 0x50) {
if (device == DIMM0) {
return smbus_read_byte(device, address);
} else if (device == 0x51) {
} else if (device == DIMM1) {
for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
if (spd_table[i].address == address)
return spd_table[i].data;

83
src/mainboard/supermicro/h8dmr_fam10/spd_addr.h
View File

@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
@ -107,4 +29,3 @@ static const u8 spd_addr[] = {
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};

83
src/mainboard/supermicro/h8qme_fam10/spd_addr.h
View File

@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
@ -113,4 +35,3 @@ static const u8 spd_addr[] = {
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif
};

12
src/mainboard/supermicro/x6dai_g/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

12
src/mainboard/supermicro/x6dhe_g/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

12
src/mainboard/supermicro/x6dhe_g2/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

12
src/mainboard/supermicro/x6dhr_ig/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

12
src/mainboard/supermicro/x6dhr_ig2/debug.c
View File

@ -1,6 +1,4 @@
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x57
#define SMBUS_MEM_DEVICE_INC 1
#include <spd.h>
static void print_reg(unsigned char index)
{
@ -271,8 +269,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM7) {
int status = 0;
int i;
print_debug("\n");
@ -296,7 +294,7 @@ void dump_spd_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}
@ -324,7 +322,7 @@ void dump_ipmi_registers(void)
print_debug_hex8(status);
print_debug_char(' ');
}
device += SMBUS_MEM_DEVICE_INC;
device++;
print_debug("\n");
}
}

7
src/mainboard/thomson/ip1000/romstage.c
View File

@ -46,15 +46,16 @@
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
* socket0 (0x50), and the onboard memory is located in socket1 (0x51).
* socket0 (0x50/DIMM0), and the onboard memory is located in socket1
* (0x51/DIMM1).
*/
static inline int spd_read_byte(unsigned device, unsigned address)
{
int i;
if (device == 0x50) {
if (device == DIMM0) {
return smbus_read_byte(device, address);
} else if (device == 0x51) {
} else if (device == DIMM1) {
for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
if (spd_table[i].address == address)
return spd_table[i].data;

83
src/mainboard/tyan/s2912_fam10/spd_addr.h
View File

@ -17,87 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* romstage.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
/** This file defines the SPD addresses for the mainboard. */
#include <spd.h>
static const u8 spd_addr[] = {
//first node
@ -107,4 +29,3 @@ static const u8 spd_addr[] = {
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};

2
src/mainboard/via/epia-cn/romstage.c
View File

@ -75,7 +75,7 @@ static const struct mem_controller ctrl = {
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { 0x50 },
.channel0 = { DIMM0 },
};
void main(unsigned long bist)

2
src/mainboard/via/epia-n/romstage.c
View File

@ -50,7 +50,7 @@ static const struct mem_controller ctrl = {
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { 0x50 },
.channel0 = { DIMM0 },
};
static inline int spd_read_byte(unsigned device, unsigned address)

2
src/mainboard/via/pc2500e/romstage.c
View File

@ -51,7 +51,7 @@ static const struct mem_controller ctrl = {
.d0f4 = 0x4000,
.d0f7 = 0x7000,
.d1f0 = 0x8000,
.channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */
.channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
};
void main(unsigned long bist)

2
src/mainboard/via/vt8454c/romstage.c
View File

@ -91,7 +91,7 @@ void main(unsigned long bist)
/* Set statically so it should work with cx700 as well */
static const struct mem_controller cx700[] = {
{
.channel0 = {0x50, 0x51},
.channel0 = {DIMM0, DIMM1},
},
};

12
src/northbridge/amd/amdk8/raminit_test.c
View File

@ -268,11 +268,11 @@ static int spd_read_byte(unsigned device, unsigned address)
{
int result;
spd_count++;
if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) {
if ((device < DIMM0) || (device >= (DIMM0 + MAX_DIMMS))) {
result = -1;
}
else {
device -= 0x50;
device -= DIMM0; /* 0x50 */
if (address > 256) {
result = -1;
@ -324,8 +324,8 @@ static void raminit_main(void)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 },
.channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 },
.channel0 = { DIMM0+0, DIMM0+2, DIMM0+4, DIMM0+6 },
.channel1 = { DIMM0+1, DIMM0+3, DIMM0+5, DIMM0+7 },
},
#endif
#if SECOND_CPU
@ -335,8 +335,8 @@ static void raminit_main(void)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 },
.channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 },
.channel0 = { DIMM0+8, DIMM0+10, DIMM0+12, DIMM0+14 },
.channel1 = { DIMM0+9, DIMM0+11, DIMM0+13, DIMM0+15 },
},
#endif
};

2
src/northbridge/intel/i440bx/debug.c
View File

@ -7,7 +7,7 @@ void dump_spd_registers(void)
print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
device = DIMM0 + i;
if (device) {
int j;
print_debug("dimm: ");

4
src/northbridge/intel/i440bx/raminit.c
View File

@ -616,7 +616,7 @@ static void spd_enable_refresh(void)
reg = pci_read_config8(NB, DRAMC);
for (i = 0; i < DIMM_SOCKETS; i++) {
value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH);
value = spd_read_byte(DIMM0 + i, SPD_REFRESH);
if (value < 0)
continue;
reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
@ -750,7 +750,7 @@ static void set_dram_row_attributes(void)
for (i = 0; i < DIMM_SOCKETS; i++) {
unsigned int device;
device = DIMM_SPD_BASE + i;
device = DIMM0 + i;
bpr >>= 2;
/* First check if a DIMM is actually present. */

3
src/northbridge/intel/i440bx/raminit.h
View File

@ -24,9 +24,6 @@
/* The 440BX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
#define DIMM_SPD_BASE 0x50
/* Function prototypes. */
int spd_read_byte(unsigned int device, unsigned int address);
void sdram_set_registers(void);

8
src/northbridge/intel/i440lx/raminit.c
View File

@ -301,18 +301,18 @@ static void sdram_set_spd_registers(void)
PRINT_DEBUG("DIMM");
PRINT_DEBUG_HEX8(i);
PRINT_DEBUG(" rows: ");
PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & 0xFF);
PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & 0xFF);
PRINT_DEBUG(" rowsize: ");
PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF);
PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF);
PRINT_DEBUG(" modulesize: ");
j = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS);
j = spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS);
if (j < 0)
j = 0;
else
ds = j;
j = spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
j = spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
if (j < 0)
j = 0;

3
src/northbridge/intel/i440lx/raminit.h
View File

@ -25,7 +25,4 @@
/* The 440LX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
#define DIMM_SPD_BASE 0x50
#endif /* RAMINIT_H */

2
src/northbridge/intel/i82810/debug.c
View File

@ -7,7 +7,7 @@ void dump_spd_registers(void)
print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
device = DIMM0 + i;
if (device) {
int j;
print_debug("dimm: ");

20
src/northbridge/intel/i82810/raminit.c
View File

@ -255,12 +255,12 @@ static void spd_set_dram_size(void)
for (i = 0; i < DIMM_SOCKETS; i++) {
/* First check if a DIMM is actually present. */
if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
if (smbus_read_byte(DIMM0 + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
print_debug("\n");
dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
dimm_size = smbus_read_byte(DIMM0 + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
@ -293,7 +293,7 @@ static void spd_set_dram_size(void)
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) ==
0xff) {
print_debug("DIMM is dual-sided\n");
dimm_size += 2;
@ -361,20 +361,18 @@ static void set_dram_buffer_strength(void)
/* Check first slot. */
d0.size = d0.ds = d0.ss = 0;
if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
== SPD_MEMORY_TYPE_SDRAM) {
d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
if (smbus_read_byte(DIMM0, SPD_MEMORY_TYPE) == SPD_MEMORY_TYPE_SDRAM) {
d0.size = smbus_read_byte(DIMM0, SPD_BANK_DENSITY);
d0.ds = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) > 1;
d0.ss = !d0.ds;
}
/* Check second slot. */
d1.size = d1.ds = d1.ss = 0;
if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
if (smbus_read_byte(DIMM0 + 1, SPD_MEMORY_TYPE)
== SPD_MEMORY_TYPE_SDRAM) {
d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
SPD_NUM_DIMM_BANKS) > 1;
d1.size = smbus_read_byte(DIMM0 + 1, SPD_BANK_DENSITY);
d1.ds = smbus_read_byte(DIMM0 + 1, SPD_NUM_DIMM_BANKS) > 1;
d1.ss = !d1.ds;
}

3
src/northbridge/intel/i82810/raminit.h
View File

@ -24,9 +24,6 @@
/* The 82810 supports max. 2 dual-sided DIMMs. */
#define DIMM_SOCKETS 2
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
/* Function prototypes. */
void sdram_set_registers(void);
void sdram_set_spd_registers(void);

12
src/northbridge/intel/i82830/raminit.c
View File

@ -101,16 +101,16 @@ static void initialize_dimm_rows(void)
switch (row) {
case 0:
device = DIMM_SPD_BASE;
device = DIMM0;
break;
case 1:
device = DIMM_SPD_BASE;
device = DIMM0;
break;
case 2:
device = DIMM_SPD_BASE + 1;
device = DIMM0 + 1;
break;
case 3:
device = DIMM_SPD_BASE + 1;
device = DIMM0 + 1;
break;
}
@ -224,7 +224,7 @@ static void set_dram_row_boundaries(void)
for (i = 0; i < DIMM_SOCKETS; i++) {
struct dimm_size sz;
unsigned device;
device = DIMM_SPD_BASE + i;
device = DIMM0 + i;
drb1 = 0;
drb2 = 0;
@ -316,7 +316,7 @@ static void set_dram_row_attributes(void)
for (i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
device = DIMM0 + i;
/* First check if a DIMM is actually present. */
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {

3
src/northbridge/intel/i82830/raminit.h
View File

@ -27,7 +27,4 @@
/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */

4
src/northbridge/intel/i855/raminit.h
View File

@ -28,9 +28,6 @@
/* The i855 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
struct mem_controller {
device_t d0;
uint16_t channel0[DIMM_SOCKETS];
@ -38,5 +35,4 @@ struct mem_controller {
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */

11
src/northbridge/intel/i945/debug.c
View File

@ -19,6 +19,7 @@
* MA 02110-1301 USA
*/
#include <spd.h>
#include <lib.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
@ -26,10 +27,6 @@
#include <console/console.h>
#include "i945.h"
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
void print_pci_devices(void)
{
device_t dev;
@ -88,8 +85,8 @@ void dump_pci_devices(void)
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
device = DIMM0;
while(device <= DIMM3) {
int status = 0;
int i;
printk(BIOS_DEBUG, "\ndimm %02x", device);
@ -105,7 +102,7 @@ void dump_spd_registers(void)
}
printk(BIOS_DEBUG, "%02x ", status);
}
device += SMBUS_MEM_DEVICE_INC;
device++;
printk(BIOS_DEBUG, "\n");
}
}

45
src/northbridge/intel/i945/raminit.c
View File

@ -323,15 +323,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
/**
* i945 supports two DIMMs, in two configurations:
*
* - single channel with two dimms
* - dual channel with one dimm per channel
* - single channel with two DIMMs
* - dual channel with one DIMM per channel
*
* In practice dual channel mainboards have their spd at 0x50, 0x52
* whereas single channel configurations have their spd at 0x50/x51
* In practice dual channel mainboards have their SPD at 0x50/0x52
* whereas single channel configurations have their SPD at 0x50/0x51.
*
* The capability register knows a lot about the channel configuration
* but for now we stick with the information we gather from the SPD
* ROMs
* but for now we stick with the information we gather via SPD.
*/
if (sdram_capabilities_dual_channel()) {
@ -362,7 +361,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
*/
for (i=0; i<(2 * DIMM_SOCKETS); i++) {
u8 reg8, device = DIMM_SPD_BASE + i;
u8 reg8, device = DIMM0 + i;
/* Initialize the socket information with a sane value */
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@ -453,7 +452,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo)
continue;
/* Is the current DIMM a stacked DIMM? */
if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
sysinfo->package = 1;
}
}
@ -470,7 +469,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
for (i=0; i<2*DIMM_SOCKETS; i++) {
if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
}
if(!cas_mask) {
@ -531,7 +530,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
continue;
}
current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
while (current_cas_mask) {
int highest_supported_cas = 0, current_cas = 0;
@ -553,11 +552,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
idx = highest_supported_cas - current_cas;
PRINTK_DEBUG("idx=%d, ", idx);
PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
PRINTK_DEBUG(": OK\n");
break;
}
@ -621,7 +620,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
if (!reg8) {
die("Invalid tRAS value.\n");
}
@ -661,7 +660,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
if (!reg8) {
die("Invalid tRP value.\n");
}
@ -702,7 +701,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
if (!reg8) {
die("Invalid tRCD value.\n");
}
@ -742,7 +741,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
if (!reg8) {
die("Invalid tWR value.\n");
}
@ -823,7 +822,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
/* 15.6us */
if (!refresh)
@ -851,7 +850,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
}
}
@ -1471,9 +1470,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
sz = sdram_get_dimm_size(DIMM0 + i);
sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
if (sz.side1 < 30)
die("DDR-II rank size smaller than 128MB is not supported.\n");
@ -1565,7 +1564,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
continue;
}
device = DIMM_SPD_BASE + i;
device = DIMM0 + i;
value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
columnsrows = (value & 0x0f);

1
src/northbridge/intel/i945/raminit.h
View File

@ -22,7 +22,6 @@
#define DIMM_SOCKETS 2
#define DIMM_SPD_BASE 0x50
#define DIMM_TCO_BASE 0x30
/* Burst length is always 8 */

58
src/northbridge/via/cn400/raminit.c
View File

@ -174,17 +174,15 @@ static void ddr_ram_setup(void)
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0;
b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
//print_val("Detecting Memory\nNumber of Banks ",b);
// Only supporting 4 bank chips just now
if( b == 4 ){
/*
Read SPD byte 3, Number of row addresses.
*/
/* Read SPD byte 3, Number of row addresses. */
c = 0x01;
bank = 0x40;
b = smbus_read_byte(0x50, SPD_NUM_ROWS);
b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
//print_val("\nNumber of Rows ", b);
if( b >= 0x0d ){ // 256/512Mb
@ -194,19 +192,15 @@ static void ddr_ram_setup(void)
else
bank = 0x44;
/*
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
/* Read SPD byte 13, Primary DRAM width. */
b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
//print_val("\nPrimary DRAM width", b);
if( b != 4 ) // not 64/128Mb (x4)
c = 0x81; // 256Mb
}
/*
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
/* Read SPD byte 4, Number of column addresses. */
b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
//print_val("\nNo Columns ",b);
if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
@ -238,7 +232,7 @@ static void ddr_ram_setup(void)
// Read SPD byte 31 Module bank density
//c = 0;
b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
if( b & 0x02 )
{
c = 0x40; // 2GB
@ -278,7 +272,7 @@ static void ddr_ram_setup(void)
pci_write_config8(ctrl.d0f3, 0x40, c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
//print_val("\nNo Physical Banks ",b);
if( b == 2)
@ -307,7 +301,7 @@ static void ddr_ram_setup(void)
ma = bank;
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
/* print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
@ -316,30 +310,30 @@ static void ddr_ram_setup(void)
if(b & 0x10)
print_debug("3");
c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
print_val("\nCycle time at CL X (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
print_val("\nCycle time at CL X-0.5 (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
print_val("\nCycle time at CL X-1 (nS)", c);
*/
/* Scaling of Cycle Time SPD data */
/* 7 4 3 0 */
/* ns x0.1ns */
bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if( b & 0x10 ){ // DDR offering optional CAS 3
//print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
//print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
@ -348,7 +342,7 @@ static void ddr_ram_setup(void)
//print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
@ -383,7 +377,7 @@ static void ddr_ram_setup(void)
Read SPD byte 27, min row pre-charge time.
*/
b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
//print_val("\ntRP ",b);
if ( b >= (5 * bank)) {
@ -402,7 +396,7 @@ static void ddr_ram_setup(void)
Read SPD byte 29, min row pre-charge time.
*/
b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
//print_val("\ntRCD ",b);
if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
@ -419,7 +413,7 @@ static void ddr_ram_setup(void)
/* tRAS is in whole ns */
bank = bank >> 2;
b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
//print_val("\ntRAS ",b);
//print_val("\nBank ", bank);
if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
@ -438,7 +432,7 @@ static void ddr_ram_setup(void)
/*
DRAM Clock Device 0 Fn 3 Offset 68
*/
bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
/* Setup DRAM Cycle Time */
if ( bank <= 0x50 )
@ -469,7 +463,7 @@ static void ddr_ram_setup(void)
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0x0F;
b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
if( b == 4) c |= 0x80;
else if (b == 2) c |= 0x40;
@ -520,7 +514,7 @@ static void ddr_ram_setup(void)
/* SPD byte 5 # of physical banks */
b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
c = b | 0x40;
pci_write_config8(ctrl.d0f3, 0xb0, c);
@ -532,7 +526,7 @@ static void ddr_ram_setup(void)
pci_write_config8(ctrl.d0f3, 0x48, ma);
udelay(200);
c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS);
c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
c &= 0x08;
if ( c == 0x08 )
{
@ -673,7 +667,7 @@ static void ddr_ram_setup(void)
pci_write_config8(ctrl.d0f3, 0xED, 0x11);
/* SPD byte 5 # of physical banks */
b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
/* determine low bond */
if( b == 2)
@ -795,7 +789,7 @@ static void ddr_ram_setup(void)
*/
//c = pci_read_config8(ctrl.d0f3, 0x68);
//c &= 0x07;
//b = smbus_read_byte(0x50, SPD_REFRESH);
//b = smbus_read_byte(DIMM0, SPD_REFRESH);
//print_val("SPD_REFRESH = ", b);
pci_write_config8(ctrl.d0f3,0x6a,0x65);

16
src/northbridge/via/vt8601/raminit.c
View File

@ -34,6 +34,8 @@ it with the version available from LANL.
*/
/* converted to C 9/2003 Ron Minnich */
#include <spd.h>
/* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB
* frequency is 133MHz. If your CPU runs at another bus speed, you
* might need to change some of register values.
@ -178,8 +180,8 @@ static unsigned long spd_module_size(unsigned char slot)
/* we may run out of registers ... */
unsigned int banks, rows, cols;
unsigned int value = 0;
/* unsigned int module = ((0x50 + slot) << 1) + 1; */
unsigned int module = 0x50 + slot;
/* unsigned int module = ((DIMM0 + slot) << 1) + 1; */
unsigned int module = DIMM0 + slot;
/* is the module there? if byte 2 is not 4, then we'll assume it
* is useless.
@ -220,7 +222,7 @@ static unsigned long spd_module_size(unsigned char slot)
#if 0
static int spd_num_chips(unsigned char slot)
{
unsigned int module = 0x50 + slot;
unsigned int module = DIMM0 + slot;
unsigned int width;
width = smbus_read_byte(module, 13);
@ -236,13 +238,13 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
unsigned char Trp = 1, Tras = 1, casl = 2, val;
unsigned char timing = 0xe4;
/* read Trp */
val = smbus_read_byte(0x50, 27);
val = smbus_read_byte(DIMM0, 27);
if (val < 2 * T133)
Trp = 1;
val = smbus_read_byte(0x50, 30);
val = smbus_read_byte(DIMM0, 30);
if (val < 5 * T133)
Tras = 0;
val = smbus_read_byte(0x50, 18);
val = smbus_read_byte(DIMM0, 18);
if (val < 8)
casl = 1;
if (val < 4)
@ -366,7 +368,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
continue;
/* Read the row densities */
size = smbus_read_byte(0x50+slot, 0x1f);
size = smbus_read_byte(DIMM0 + slot, 0x1f);
/* Set the MA map type.
*

37
src/northbridge/via/vt8623/raminit.c
View File

@ -30,6 +30,7 @@
*/
/* ported and enhanced from assembler level code in coreboot v1 */
#include <spd.h>
#include <cpu/x86/mtrr.h>
#include "raminit.h"
@ -101,7 +102,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0;
b = smbus_read_byte(0xa0,17);
b = smbus_read_byte(DIMM0,17);
print_val("Detecting Memory\nNumber of Banks ",b);
if( b != 2 ){ // not 16 Mb type
@ -109,14 +110,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
/*
Read SPD byte 3, Number of row addresses.
*/
b = smbus_read_byte(0xa0,3);
b = smbus_read_byte(DIMM0,3);
print_val("\nNumber of Rows ",b);
if( b >= 0x0d ){ // not 64/128Mb (rows <=12)
/*
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0xa0,13);
b = smbus_read_byte(DIMM0,13);
print_val("\nPriamry DRAM width",b);
if( b != 4 ) // mot 64/128Mb (x4)
c = 0x80; // 256Mb
@ -127,7 +128,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0xa0,4);
b = smbus_read_byte(DIMM0,4);
print_val("\nNo Columns ",b);
if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
@ -149,7 +150,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
// Read SPD byte 31 Module bank density
c = 0;
b = smbus_read_byte(0xa0,31);
b = smbus_read_byte(DIMM0,31);
if( b & 0x02 ) c = 0x80; // 2GB
else if( b & 0x01) c = 0x40; // 1GB
else if( b & 0x80) c = 0x20; // 512Mb
@ -166,7 +167,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
// set bank zero size
pci_write_config8(north,0x5a,c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(0xa0,5);
b = smbus_read_byte(DIMM0,5);
print_val("\nNo Physical Banks ",b);
if( b == 2)
@ -180,7 +181,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0xa0,18);
b = smbus_read_byte(DIMM0,18);
print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
@ -188,9 +189,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
print_debug("2.5 ");
if(b & 0x10)
print_debug("3");
print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
print_val("\nCycle time at CL X (nS)",smbus_read_byte(DIMM0,9));
print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(DIMM0,23));
print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(DIMM0,25));
if( b & 0x10 ){ // DDR offering optional CAS 3
@ -198,13 +199,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
print_debug("\nWe can do CAS 2");
c = 0x10;
}
@ -213,7 +214,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
print_debug("\nWe can do CAS 2");
c = 0x10;
}
@ -253,7 +254,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 27, min row pre-charge time.
*/
b = smbus_read_byte(0xa0,27);
b = smbus_read_byte(DIMM0,27);
print_val("\ntRP ",b);
if( b > 0x3c ) // set tRP = 3T
c |= 0x80;
@ -265,7 +266,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 29, min row pre-charge time.
*/
b = smbus_read_byte(0xa0,29);
b = smbus_read_byte(DIMM0,29);
print_val("\ntRCD ",b);
if( b > 0x3c ) // set tRCD = 3T
c |= 0x04;
@ -277,7 +278,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 30, device min active to pre-charge time.
*/
b = smbus_read_byte(0xa0,30);
b = smbus_read_byte(DIMM0,30);
print_val("\ntRAS ",b);
if( b > 0x25 ) // set tRAS = 6T
c |= 0x40;
@ -288,7 +289,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 17, Number of banks on SDRAM device.
*/
b = smbus_read_byte(0xa0,17);
b = smbus_read_byte(DIMM0,17);
if( b == 4) c |= 0x02;
else if (b == 2) c |= 0x01;
@ -342,7 +343,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
pci_write_config8(north,0x6d,0x044);
pci_write_config8(north,0x67,0x3a);
b = smbus_read_byte(0xa0,5); // SPD byte 5 # of physical banks
b = smbus_read_byte(DIMM0,5); // SPD byte 5 # of physical banks
if( b > 1) {
// Increase drive control when there is more than 1 physical bank
pci_write_config8(north,0x6c,0x84); // Drive control: MA, DQS, MD/CKE

7
src/northbridge/via/vx800/detection.c
View File

@ -19,14 +19,9 @@
/* FIXME this should go away */
static const struct mem_controller ctrl = {
.channel0 = {0x50, 0x51},
.channel0 = {DIMM0, DIMM1},
};
#define SMBUS_ADDR_CH_A_1 0xA0 /* Dimmx */
#define SMBUS_ADDR_CH_A_2 0xA2 /* Dimmx */
#define SMBUS_ADDR_CH_B_1 0xA4 /* Dimmx */
#define SMBUS_ADDR_CH_B_2 0xA6 /* Dimmx */
/* read data */
CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 *Buf);
void DRAMCmdRate(DRAM_SYS_ATTR *DramAttr);

2
src/southbridge/via/vt8235/vt8235_early_smbus.c
View File

@ -174,7 +174,7 @@ static unsigned char smbus_read_byte(unsigned char devAdr,
outb(bIndex, SMBUS_IO_BASE+3);
/* set slave address */
outb(devAdr | 0x01, SMBUS_IO_BASE+4);
outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4);
/* start */
outb(0x48, SMBUS_IO_BASE+2);