vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -141,7 +141,9 @@ typedef enum {
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LpDdr2MemType, ///< Assign 28 to LPDDR2
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LpDdr2MemType, ///< Assign 28 to LPDDR2
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LpDdr3MemType, ///< Assign 29 to LPDDR3
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LpDdr3MemType, ///< Assign 29 to LPDDR3
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LpDdr4MemType, ///< Assign 30 to LPDDR4
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LpDdr4MemType, ///< Assign 30 to LPDDR4
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LpDdr5MemType, ///< Assign 31 to LPDDR5
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Ddr5MemType = 0x22, ///< Assign 34 to DDR5
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LpDdr5MemType, ///< Assign 35 to LPDDR5
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LpDdr5xMemType, ///< Assign 36 to LPDDR5X
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} DMI_T17_MEMORY_TYPE;
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} DMI_T17_MEMORY_TYPE;
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/// DMI Type 17 offset 13h - Type Detail
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/// DMI Type 17 offset 13h - Type Detail
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