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vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE 

Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.

BUG=b:239000826
TEST=Build and verify with other patches in train

Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Matt DeVillier 2022-08-22 17:07:58 -05:00 committed by Martin Roth
parent 93447c42a8
commit d77525b5bd
1 changed files with 3 additions and 1 deletions
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4
src/vendorcode/amd/fsp/mendocino/dmi_info.h
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@ -141,7 +141,9 @@ typedef enum {
LpDdr2MemType, ///< Assign 28 to LPDDR2
LpDdr3MemType, ///< Assign 29 to LPDDR3
LpDdr4MemType, ///< Assign 30 to LPDDR4
LpDdr5MemType, ///< Assign 31 to LPDDR5
Ddr5MemType = 0x22, ///< Assign 34 to DDR5
LpDdr5MemType, ///< Assign 35 to LPDDR5
LpDdr5xMemType, ///< Assign 36 to LPDDR5X
} DMI_T17_MEMORY_TYPE;
/// DMI Type 17 offset 13h - Type Detail