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ACPI: Drop redundant ChromeOS setup for GNVS 

Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.

Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-06-17 08:15:39 +03:00 committed by Nico Huber
parent 81b8472237
commit d77b5e9f99
19 changed files with 16 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/acpi/chromeos-gnvs.c
View File

@ -4,12 +4,6 @@
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
/* Remove once implemented on platform code. */
__weak void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
{
return NULL;
}
void gnvs_assign_chromeos(void)
{
chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());

7
src/mainboard/google/link/acpi_tables.c
View File

@ -2,8 +2,6 @@
#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include "thermal.h"
void acpi_create_gnvs(struct global_nvs *gnvs)
@ -16,11 +14,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
gnvs->tmps = CTDP_SENSOR_ID;
gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;

7
src/mainboard/google/slippy/acpi_tables.c
View File

@ -3,8 +3,6 @@
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <ec/google/chromeec/ec.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/nvs.h>
@ -23,11 +21,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
gnvs->tmps = TEMPERATURE_SENSOR_ID;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;

6
src/soc/amd/picasso/acpi.c
View File

@ -396,12 +396,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
void acpi_create_gnvs(struct global_nvs *gnvs)
{
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&gnvs->chromeos);
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
gnvs->gpei = ~0ULL;

6
src/soc/amd/stoneyridge/acpi.c
View File

@ -164,12 +164,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
void acpi_create_gnvs(struct global_nvs *gnvs)
{
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&gnvs->chromeos);
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
gnvs->gpei = ~0ULL;

11
src/soc/intel/alderlake/acpi.c
View File

@ -9,7 +9,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@ -289,16 +288,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

6
src/soc/intel/apollolake/acpi.c
View File

@ -77,12 +77,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
struct soc_intel_apollolake_config *cfg;
cfg = config_of_soc();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&gnvs->chromeos);
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;

14
src/soc/intel/baytrail/acpi.c
View File

@ -21,9 +21,6 @@
#include <soc/pattrs.h>
#include <soc/pm.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
#define MWAIT_RES(state, sub_state) \
{ \
.addrl = (((state) << 4) | (sub_state)), \
@ -69,17 +66,6 @@ void acpi_init_gnvs(struct global_nvs *gnvs)
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else {
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
}
}
int acpi_sci_irq(void)

13
src/soc/intel/braswell/acpi.c
View File

@ -11,7 +11,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>
#include <drivers/intel/gma/opregion.h>
#include <soc/acpi.h>
#include <soc/gfx.h>
@ -24,7 +23,6 @@
#include <soc/pm.h>
#include <string.h>
#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
#define MWAIT_RES(state, sub_state) \
@ -72,17 +70,6 @@ void acpi_init_gnvs(struct global_nvs *gnvs)
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else {
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
}
}
int acpi_sci_irq(void)

13
src/soc/intel/broadwell/pch/lpc.c
View File

@ -13,8 +13,6 @@
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/iobp.h>
@ -618,17 +616,6 @@ static void southcluster_inject_dsdt(const struct device *device)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else {
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
}
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);

13
src/soc/intel/cannonlake/acpi.c
View File

@ -8,7 +8,6 @@
#include <console/console.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@ -20,7 +19,6 @@
#include <soc/pm.h>
#include <soc/systemagent.h>
#include <string.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
#include "chip.h"
@ -194,17 +192,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else {
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

11
src/soc/intel/elkhartlake/acpi.c
View File

@ -9,7 +9,6 @@
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/acpi.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
@ -257,16 +256,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

12
src/soc/intel/icelake/acpi.c
View File

@ -6,7 +6,6 @@
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@ -18,7 +17,6 @@
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
#include <string.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
/*
@ -189,16 +187,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

11
src/soc/intel/jasperlake/acpi.c
View File

@ -9,7 +9,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@ -284,16 +283,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

13
src/soc/intel/skylake/acpi.c
View File

@ -12,7 +12,6 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/common/common.h>
#include <cpu/intel/turbo.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/sgx.h>
@ -30,7 +29,6 @@
#include <soc/systemagent.h>
#include <string.h>
#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <wrdd.h>
#include <device/pci_ops.h>
@ -168,17 +166,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else {
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

11
src/soc/intel/tigerlake/acpi.c
View File

@ -9,7 +9,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
@ -284,16 +283,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (CONFIG(CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
if (CONFIG(EC_GOOGLE_CHROMEEC)) {
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
} else
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = config->dptf_enable;

10
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -647,6 +647,11 @@ size_t gnvs_size_of_array(void)
return sizeof(struct global_nvs);
}
void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
{
return &gnvs->chromeos;
}
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
@ -659,11 +664,6 @@ void southbridge_inject_dsdt(const struct device *dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
#if CONFIG(CHROMEOS)
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
#endif
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);

6
src/southbridge/intel/i82801ix/lpc.c
View File

@ -458,6 +458,12 @@ size_t gnvs_size_of_array(void)
return sizeof(struct global_nvs);
}
/* To build emulation/qemu-q35 with CHROMEOS. */
void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
{
return 0;
}
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();

11
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -690,6 +690,11 @@ uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs)
return &gnvs->cbmc;
}
void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
{
return &gnvs->chromeos;
}
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs;
@ -703,12 +708,6 @@ void southbridge_inject_dsdt(const struct device *dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
#if CONFIG(CHROMEOS)
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
#endif
/* Add it to DSDT. */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32)gnvs);