diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index ac340a62af..2d42ad9ad9 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -51,6 +51,12 @@
 #define  ACPI_GPE0_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
 #define  ACPI_PM_TMR_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
 #define SMB_BASE_ADDR			0xb00
+#define PM2_INDEX			0xcd0
+#define PM2_DATA			0xcd1
+#define BIOSRAM_INDEX			0xcd4
+#define BIOSRAM_DATA			0xcd5
+#define PM_INDEX			0xcd6
+#define PM_DATA				0xcd7
 #define AB_INDX				0xcd8
 #define AB_DATA				(AB_INDX+4)
 #define SYS_RESET			0xcf9
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index d9016bc427..73e9b6fcd5 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -30,14 +30,7 @@
 #define PSP_BAR_ENABLES			0x48
 #define  PSP_MAILBOX_BAR_EN		0x10
 
-/* Power management index/data registers */
-#define BIOSRAM_INDEX			0xcd4
-#define BIOSRAM_DATA			0xcd5
-#define PM_INDEX			0xcd6
-#define PM_DATA				0xcd7
-#define PM2_INDEX			0xcd0
-#define PM2_DATA			0xcd1
-
+/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define   FORCE_STPCLK_RETRY		BIT(24)