soc/amd/common: Refactor SMBus base arguments
Replace SMBus base addresses with proper symbols. Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42074 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -126,10 +126,6 @@
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#define ACPIMMIO_ACDCTMR_BANK 0x1d00
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#define ACPIMMIO_AOAC_BANK 0x1e00
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/* FIXME: Passing host base for SMBUS is not long-term solution. */
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#define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK)
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#define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK)
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#endif
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#endif /* AMD_BLOCK_ACPIMMIO_MAP_H */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio_map.h>
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#include <amdblocks/acpimmio.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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@ -27,9 +27,9 @@ static u32 get_sm_mmio(struct device *dev)
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x90);
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if (res->base == SMB_BASE_ADDR)
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return ACPIMMIO_SMBUS_BASE;
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return (uintptr_t)acpimmio_smbus;
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return ACPIMMIO_ASF_BASE;
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return (uintptr_t)acpimmio_asf;
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}
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static int lsmbus_recv_byte(struct device *dev)
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@ -4,8 +4,8 @@
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#include <console/console.h>
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#include <device/smbus_host.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpimmio_map.h>
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#include <amdblocks/smbus.h>
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#include <soc/southbridge.h>
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/*
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* Between 1-10 seconds, We should never timeout normally
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@ -13,37 +13,27 @@
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*/
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#define SMBUS_TIMEOUT (100 * 1000 * 10)
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static u8 controller_read8(uintptr_t base, u8 reg)
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/* FIXME: Passing host base for SMBUS is not long-term solution.
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It is possible to have multiple buses behind same host. */
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static u8 controller_read8(const uintptr_t base, const u8 reg)
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{
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switch (base) {
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case ACPIMMIO_SMBUS_BASE:
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return smbus_read8(reg);
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case ACPIMMIO_ASF_BASE:
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return asf_read8(reg);
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default:
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printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n",
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base);
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}
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return 0xff;
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return read8((void *)(base + reg));
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}
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static void controller_write8(uintptr_t base, u8 reg, u8 val)
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static void controller_write8(const uintptr_t base, const u8 reg, const u8 val)
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{
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switch (base) {
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case ACPIMMIO_SMBUS_BASE:
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smbus_write8(reg, val);
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break;
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case ACPIMMIO_ASF_BASE:
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asf_write8(reg, val);
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break;
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default:
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printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n",
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base);
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}
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write8((void *)(base + reg), val);
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}
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static int smbus_wait_until_ready(uintptr_t mmio)
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{
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if ((mmio != (uintptr_t)acpimmio_smbus) &&
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(mmio != (uintptr_t)acpimmio_asf)) {
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printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio);
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return -1;
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}
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u32 loops;
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loops = SMBUS_TIMEOUT;
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do {
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/acpimmio_map.h>
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#include <amdblocks/acpimmio.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <device/device.h>
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@ -34,7 +34,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count)
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dev_addr = (SmbusSlaveAddress >> 1);
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/* Read the first SPD byte */
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error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0);
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error = do_smbus_read_byte((uintptr_t)acpimmio_smbus, dev_addr, 0);
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if (error < 0) {
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printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
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return error;
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@ -44,7 +44,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count)
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/* Read the remaining SPD bytes using do_smbus_recv_byte for speed */
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for (index = 1 ; index < count ; index++) {
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error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr);
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error = do_smbus_recv_byte((uintptr_t)acpimmio_smbus, dev_addr);
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if (error < 0) {
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printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
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return error;
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