mb/google/octopus: Override emmc DLL values for Meep

New emmc DLL values for Meep.

BUG=b:122308271
TEST=Boot to OS on 13 Meep system

Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31021
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen 2019-01-21 10:19:46 +08:00 committed by Furquan Shaikh
parent 6b239d8e08
commit d78a202843
1 changed files with 41 additions and 0 deletions

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@ -1,5 +1,46 @@
chip soc/intel/apollolake chip soc/intel/apollolake
# EMMC Tx CMD Delay
# Refer to EDS-Vol2-16.32.
# [14:8] steps of delay for DDR mode, each 125ps.
# [6:0] steps of delay for SDR mode, each 125ps.
register "emmc_tx_cmd_cntl" = "0x505"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-16.33.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0b0d"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-16.34.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x1c2a2a2a"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-16.35.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00171a1a"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-16.37.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10028"
# EMMC Rx Strobe Delay
# Refer to EDS-Vol2-16.36.
# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
register "emmc_rx_strobe_cntl" = "0x0b0b"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |