diff --git a/util/flashrom/README b/util/flashrom/README
index 7be37c74c7..9f842ff508 100644
--- a/util/flashrom/README
+++ b/util/flashrom/README
@@ -58,6 +58,7 @@ no LinuxBIOS table is found:
 * GIGABYTE GA-M57SLI-S4 v2.0: use -m gigabyte:m57sli
 * GIGABYTE GA-M61P-S3: use -m gigabyte:m61p
 * MSI K8N Neo3: use -m msi:k8n-neo3
+* Acorp 6A815EPD: use -m acorp:6a815epd
 
 
 ROM Layout Support
diff --git a/util/flashrom/board_enable.c b/util/flashrom/board_enable.c
index 78749634ae..13c4f1f5e3 100644
--- a/util/flashrom/board_enable.c
+++ b/util/flashrom/board_enable.c
@@ -322,6 +322,32 @@ static int board_epox_ep_bx3(const char *name)
 	return 0;
 }
 
+/**
+ * Suited for Acorp 6A815EPD
+ */
+static int board_acorp_6a815epd(const char *name)
+{
+	struct pci_dev *dev;
+	uint16_t port;
+	uint8_t val;
+
+	dev = pci_dev_find(0x8086, 0x2440);     /* Intel ICH2 LPC */
+	if (!dev) {
+		fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n");
+		return -1;
+	}
+
+	/* Use GPIOBASE register to find where the GPIO is mapped. */
+	port = (pci_read_word(dev, 0x58) & 0xFF80) + 0xE;
+
+	val = inb(port);
+	val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
+	val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */
+	outb(val, port);
+
+	return 0;
+}
+
 /**
  * We use 2 sets of IDs here, you're free to choose which is which. This
  * is to provide a very high degree of certainty when matching a board on
@@ -376,6 +402,8 @@ struct board_pciid_enable board_pciid_enables[] = {
 	 "ibm", "x3455", "IBM x3455", board_ibm_x3455},
 	{0x8086, 0x7110, 0x0000, 0x0000, 0x8086, 0x7190, 0x0000, 0x0000,
 	 "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3},
+	{0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33,
+	 "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd},
 	{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL}	/* Keep this */
 };