diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index dc70085dd0..f5f3eeacdf 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index b46e34cf83..5a64648cd1 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x7"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 45229bad6d..5b6ab9f858 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -34,6 +34,7 @@ chip soc/intel/broadwell
 			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.2 on  end # PCIe Port #3 - LAN (becomes RP1)
 			device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
+			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 on  end # SMBus
 #		end
 	end
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index eae7999ea2..924e7d3c90 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index dc70085dd0..f5f3eeacdf 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -12,6 +12,8 @@ chip soc/intel/broadwell
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
+
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 710fa95cac..93445756e2 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -36,6 +36,7 @@ chip soc/intel/broadwell
 			device pci 1c.0 off end # PCIe Port #1
 			device pci 1c.2 on  end # PCIe Port #3
 			device pci 1d.0 off end # USB2 EHCI
+			device pci 1f.2 on  end # SATA Controller
 #		end
 	end
 end