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soc/amd/picasso: Add GRXS and GTXS method 

Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.

BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Eric Lai 2020-12-28 15:32:54 +08:00 committed by Felix Held
parent 7cee566161
commit d7a364393a
2 changed files with 58 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
src/soc/amd/common/acpi/gpio_bank_lib.asl
View File

@ -2,6 +2,8 @@
#include <soc/iomap.h>
#define GPIO_INPUT_SHIFT 16
#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT)
#define GPIO_OUTPUT_SHIFT 22
#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
@ -148,3 +150,35 @@ Method (CTXS, 1, Serialized)
}
VAL0 &= ~GPIO_OUTPUT_VALUE
}
/*
* Get GPIO Input Value
* Arg0 - GPIO Number
*/
Method (GRXS, 1, Serialized)
{
OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
Field (GPDW, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
Local0 = (GPIO_INPUT_VALUE & VAL0) >> GPIO_INPUT_SHIFT
Return (Local0)
}
/*
* Get GPIO Output Value
* Arg0 - GPIO Number
*/
Method (GTXS, 1, Serialized)
{
OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
Field (GPDW, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
Local0 = (GPIO_OUTPUT_VALUE & VAL0) >> GPIO_OUTPUT_SHIFT
Return (Local0)
}

77
src/soc/amd/picasso/acpi.c
View File

@ -432,59 +432,6 @@ void southbridge_inject_dsdt(const struct device *device)
}
}
static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)
{
/*
* Store (\_SB.GPR2 (addr), Local5)
* \_SB.GPR2 is used to read control byte 2 from control register.
* / It is defined in gpio_lib.asl.
*/
acpigen_write_store();
acpigen_emit_namestring("\\_SB.GPR2");
acpigen_write_integer(addr);
acpigen_emit_byte(LOCAL5_OP);
}
static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
uintptr_t addr = gpio_get_address(gpio_num);
acpigen_soc_get_gpio_in_local5(addr);
/* If (And (Local5, mask)) */
acpigen_write_if_and(LOCAL5_OP, mask);
/* Store (One, Local0) */
acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
acpigen_pop_len(); /* If */
/* Else */
acpigen_write_else();
/* Store (Zero, Local0) */
acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
acpigen_pop_len(); /* Else */
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);
}
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
@ -498,6 +445,30 @@ static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
return 0;
}
static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
{
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
/* Store (op (gpio_num), Local0) */
acpigen_write_store();
acpigen_soc_gpio_op(op, gpio_num);
acpigen_emit_byte(LOCAL0_OP);
return 0;
}
int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num);
}
int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num);
}
int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
{
return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num);