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This patch enables SB700 option PrefetchEnSPIFromHost in early setup. 

It affects only systems booting from SPI flash, not those booting from
LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
lines from the flash chip. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2010-10-18 04:01:12 +00:00
parent c104cb0d9d
commit d7acdfb44a
1 changed files with 5 additions and 0 deletions
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5
src/southbridge/amd/sb700/sb700_early_setup.c
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@ -129,6 +129,11 @@ static void sb700_lpc_init(void)
reg8 |= (1 << 5) | (1 << 6); reg8 |= (1 << 5) | (1 << 6);
pci_write_config8(dev, 0x47, reg8); pci_write_config8(dev, 0x47, reg8);
/* Enable PrefetchEnSPIFromHost to speed up SPI flash read (does not affect LPC) */
reg8 = pci_read_config8(dev, 0xbb);
reg8 |= 1 << 0;
pci_write_config8(dev, 0xbb, reg8);
/* SuperIO, LPC ROM */ /* SuperIO, LPC ROM */
reg8 = pci_read_config8(dev, 0x48); reg8 = pci_read_config8(dev, 0x48);
/* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */