mb/google/x86-boards: Get rid of power button device in coreboot
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from all google mainboards and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works correctly on nautilus. Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -16,14 +16,6 @@
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#include <variant/onboard.h>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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}
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Scope (\_SB.PCI0.RP01)
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{
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Device (WLAN)
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@ -16,14 +16,6 @@
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#include <onboard.h>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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}
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/*
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* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
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*/
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@ -27,11 +27,6 @@ Scope (\_SB) {
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}
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}
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Device (PWRB)
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{
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Name (_HID, EisaId("PNP0C0C"))
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}
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Device (TPAD)
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{
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Name (_ADR, 0x0)
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@ -17,15 +17,6 @@
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#include <variant/onboard.h>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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Name (_UID, 1)
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}
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}
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Scope (\_SB.GPNC)
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{
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Method (_AEI, 0, Serialized) // _AEI: ACPI Event Interrupts
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@ -36,10 +36,6 @@ DefinitionBlock(
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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Device (PCI0)
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{
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#include <soc/intel/skylake/acpi/systemagent.asl>
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@ -36,10 +36,6 @@ DefinitionBlock(
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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Device (PCI0)
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{
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#include <soc/intel/skylake/acpi/systemagent.asl>
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@ -13,13 +13,5 @@
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* GNU General Public License for more details.
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*/
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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/* Variant-specific ACPI, including USB port defs */
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#include <variant/acpi/mainboard.asl>
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@ -16,14 +16,6 @@
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#include <mainboard/google/jecht/onboard.h>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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}
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/*
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* LAN connected to Root Port 3, becomes Root Port 1 after coalesce
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*/
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@ -56,11 +56,6 @@ DefinitionBlock (
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/* IRQ Routing mapping for this platform (in \_SB scope) */
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#include <variant/acpi/routing.asl>
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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}
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/* Describe the SOC */
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#include <soc.asl>
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@ -19,7 +19,6 @@ Scope (\_GPE)
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Method (_L08)
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{
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/* DBGO ("\\_GPE\\_L08\n") */
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Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* EHCI USB controller PME# SCIMAP24*/
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{
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/* DBGO ("\\_GPE\\_L18\n") */
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Notify (\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* XHCI USB controller PME# SCIMAP56*/
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{
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/* DBGO ("\\_GPE\\_L1F\n") */
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Notify (\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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#include <mainboard/google/link/onboard.h>
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Scope (\_SB) {
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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Device (TPAD)
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{
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Name (_ADR, 0x0)
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}
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}
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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Device (TPAD)
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{
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Name (_ADR, 0x0)
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@ -36,10 +36,6 @@ DefinitionBlock(
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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Device (PCI0)
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{
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/* Image processing unit */
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@ -18,11 +18,6 @@
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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Name (_UID, 1)
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}
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#ifdef BOARD_TRACKPAD_IRQ
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/* Wake device for touchpad */
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Device (TPAD)
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#include <onboard.h>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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}
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#include <variant/acpi/mainboard.asl>
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/* USB port entries */
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Store (Arg0, \_SB.PCI0.LPCB.EC0.HWLO)
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}
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}
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Device (PWRB)
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{
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Name (_HID, EisaId("PNP0C0C"))
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}
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}
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#include <soc/intel/cannonlake/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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Device (PCI0)
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{
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#include <soc/intel/cannonlake/acpi/northbridge.asl>
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