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haswell: Compute disabled channel masks at runtime 

All mainboards have a non-zero SPD address to implemented DIMM slots.
Knowing this, it is possible to compute the MRC slot population masks
automatically instead of hardcoding the values on each mainboard.

Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-03 20:31:39 +02:00
parent ae4fb10240
commit d7bf3ad939
8 changed files with 15 additions and 56 deletions
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8
src/mainboard/asrock/b85m_pro4/romstage.c
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@ -30,14 +30,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->gbe_enable = 1;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 0;
pei_data->dimm_channel1_disabled = 0;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

8
src/mainboard/asrock/h81m-hds/romstage.c
View File

@ -27,14 +27,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

8
src/mainboard/google/beltino/romstage.c
View File

@ -48,14 +48,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
/* Enable 2x refresh mode */
pei_data->ddr_refresh_2x = 1;
pei_data->dq_pins_interleaved = 1;

8
src/mainboard/google/slippy/romstage.c
View File

@ -48,14 +48,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[0] = 0xff;
pei_data->spd_addresses[2] = 0xff;
pei_data->ec_present = 1;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
pei_data->max_ddr3_freq = 1600;
pei_data->usb_xhci_on_resume = 1;

8
src/mainboard/intel/baskingridge/romstage.c
View File

@ -52,14 +52,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 0;
pei_data->dimm_channel1_disabled = 0;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

8
src/mainboard/lenovo/t440p/romstage.c
View File

@ -50,14 +50,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa2;
pei_data->ec_present = 1;
pei_data->gbe_enable = 1;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 2;
pei_data->dimm_channel1_disabled = 2;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

8
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@ -28,14 +28,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
pei_data->dimm_channel0_disabled = 0;
pei_data->dimm_channel1_disabled = 0;
pei_data->ddr_refresh_2x = 1;
pei_data->max_ddr3_freq = 1600;

15
src/northbridge/intel/haswell/romstage.c
View File

@ -23,6 +23,17 @@ void __weak mb_late_romstage_setup(void)
{
}
/*
* 0 = leave channel enabled
* 1 = disable dimm 0 on channel
* 2 = disable dimm 1 on channel
* 3 = disable dimm 0+1 on channel
*/
static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
{
return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
}
/* The romstage entry point for this platform is not mainboard-specific, hence the name */
void mainboard_romstage_entry(void)
{
@ -73,6 +84,10 @@ void mainboard_romstage_entry(void)
/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
pei_data.boot_mode = wake_from_s3 ? 2 : 0;
/* Calculate unimplemented DIMM slots for each channel */
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
timestamp_add_now(TS_BEFORE_INITRAM);
report_platform_info();