GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode 

me_cleaner now allows setting a bit in the PCH straps - AltMeDisable
tells the ME to stop execution after BUP - disabling the 30 minute
watchdog - but also "breaking" the ME. The ME reports opmode = 2.

This means the ME will not respond when we wait for an acknowledgement
about the DRAM being ready. The current code waits 5 seconds for a
response, that in this case, never comes.

If the ME is reporting opmode 2, don't delay or wait for a response
from the ME.

Tested on my X220, this patch fixed the five seconds before the payload
executed. Verified using the timestamp patch.

Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Nathaniel Roach 2017-09-09 19:59:07 +08:00 committed by Martin Roth
parent 2fd9651b23
commit d7e0cb93ae
2 changed files with 19 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/southbridge/intel/bd82x6x/early_me.c
View File

@ -191,18 +191,26 @@ int intel_early_me_init_done(u8 status)
meDID = did.uma_base | (1 << 28);// | (1 << 23); meDID = did.uma_base | (1 << 28);// | (1 << 23);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
udelay(1100);
/* Must wait for ME acknowledgement */ /* Must wait for ME acknowledgement */
millisec = 0; if (opmode == ME_HFS_MODE_DEBUG) {
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; printk(BIOS_NOTICE,
while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) { "ME: ME is reporting as disabled, "
udelay(1000); "so not waiting for a response.\n");
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; } else {
millisec++; timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
udelay(100);
millisec = 0;
do {
udelay(1000);
hfs = (pci_read_config32(
PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000)
>> 24;
millisec++;
} while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
&& (millisec <= 5000));
timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
} }
timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);

2
src/southbridge/intel/bd82x6x/me_status.c
View File

@ -43,7 +43,7 @@ static const char *me_opstate_values[] = {
/* HFS[19:16] Current Operation Mode Values */ /* HFS[19:16] Current Operation Mode Values */
static const char *me_opmode_values[] = { static const char *me_opmode_values[] = {
[ME_HFS_MODE_NORMAL] = "Normal", [ME_HFS_MODE_NORMAL] = "Normal",
[ME_HFS_MODE_DEBUG] = "Debug", [ME_HFS_MODE_DEBUG] = "Debug or Disabled by AltDisableBit",
[ME_HFS_MODE_DIS] = "Soft Temporary Disable", [ME_HFS_MODE_DIS] = "Soft Temporary Disable",
[ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
[ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"