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cpu/amd/agesa/family1{0,2}: Fix indent and sync closer together 

Change-Id: If1ca90aa8050fc1b2e1c98e0fb669de1d155a949
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7543
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-11-21 12:48:39 +11:00
parent 20a41ae80b
commit d7e5008bdf
2 changed files with 47 additions and 46 deletions
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1
src/cpu/amd/agesa/family10/model_10_init.c
View File

@ -40,6 +40,7 @@ static void model_10_init(device_t dev)
u8 i;
msr_t msr;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif

92
src/cpu/amd/agesa/family12/model_12_init.c
View File

@ -37,81 +37,81 @@
static void model_12_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
u8 i;
msr_t msr;
u8 i;
msr_t msr;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
u32 siblings;
#endif
// struct node_core_id id;
// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
/* Turn on caching if we haven't already */
x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
disable_cache();
disable_cache();
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 5; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < 5; i++) {
wrmsr(MCI_STATUS + (i * 4), msr);
}
enable_cache();
enable_cache();
/* Enable the local cpu apics */
setup_lapic();
/* Enable the local cpu apics */
setup_lapic();
/* Set the processor name string */
// init_processor_name();
/* Set the processor name string */
// init_processor_name();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static struct device_operations cpu_dev_ops = {
.init = model_12_init,
.init = model_12_init,
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
{ X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
{ X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
{ X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
{ 0, 0 },
{ X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
{ X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
{ X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
{ X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
{ 0, 0 },
};
static const struct cpu_driver model_12 __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};