cpu/amd/agesa/family1{0,2}: Fix indent and sync closer together
Change-Id: If1ca90aa8050fc1b2e1c98e0fb669de1d155a949 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7543 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -40,6 +40,7 @@ static void model_10_init(device_t dev)
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u8 i;
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u8 i;
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msr_t msr;
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msr_t msr;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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u32 siblings;
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#endif
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#endif
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@ -37,81 +37,81 @@
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static void model_12_init(device_t dev)
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static void model_12_init(device_t dev)
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{
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{
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printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
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printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
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u8 i;
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u8 i;
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msr_t msr;
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msr_t msr;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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u32 siblings;
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#endif
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#endif
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// struct node_core_id id;
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// struct node_core_id id;
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// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
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// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
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// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
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// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
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/* Turn on caching if we haven't already */
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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x86_enable_cache();
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amd_setup_mtrrs();
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amd_setup_mtrrs();
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x86_mtrr_check();
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x86_mtrr_check();
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disable_cache();
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disable_cache();
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/* zero the machine check error status registers */
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.lo = 0;
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msr.hi = 0;
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msr.hi = 0;
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for (i = 0; i < 5; i++) {
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for (i = 0; i < 5; i++) {
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wrmsr(MCI_STATUS + (i * 4), msr);
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wrmsr(MCI_STATUS + (i * 4), msr);
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}
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}
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enable_cache();
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enable_cache();
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/* Enable the local cpu apics */
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/* Enable the local cpu apics */
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setup_lapic();
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setup_lapic();
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/* Set the processor name string */
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/* Set the processor name string */
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// init_processor_name();
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// init_processor_name();
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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siblings = cpuid_ecx(0x80000008) & 0xff;
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siblings = cpuid_ecx(0x80000008) & 0xff;
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if (siblings > 0) {
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr.lo |= 1 << 28;
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msr.lo |= 1 << 28;
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1 << (33 - 32);
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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}
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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#endif
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#endif
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/* DisableCf8ExtCfg */
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/* DisableCf8ExtCfg */
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msr = rdmsr(NB_CFG_MSR);
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msr = rdmsr(NB_CFG_MSR);
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msr.hi &= ~(1 << (46 - 32));
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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wrmsr(NB_CFG_MSR, msr);
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/* Write protect SMM space with SMMLOCK. */
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/* Write protect SMM space with SMMLOCK. */
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msr = rdmsr(HWCR_MSR);
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msr = rdmsr(HWCR_MSR);
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msr.lo |= (1 << 0);
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msr.lo |= (1 << 0);
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wrmsr(HWCR_MSR, msr);
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wrmsr(HWCR_MSR, msr);
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}
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}
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static struct device_operations cpu_dev_ops = {
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static struct device_operations cpu_dev_ops = {
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.init = model_12_init,
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.init = model_12_init,
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};
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};
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static struct cpu_device_id cpu_table[] = {
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
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{ X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
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{ X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
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{ X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
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{ X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
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{ X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
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{ X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
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{ X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
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{ 0, 0 },
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{ 0, 0 },
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};
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};
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static const struct cpu_driver model_12 __cpu_driver = {
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static const struct cpu_driver model_12 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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.id_table = cpu_table,
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};
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};
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