mb/google/rammus: add libgfxinit support

Add libgfxinit support for rammus. Use panel init values from VBT.

Test: build/boot rammus with libgfxinit and Tianocore payload

Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/google/poppy/Kconfig

@@ -191,6 +191,7 @@ config VARIANT_SPECIFIC_OPTIONS_RAMMUS
 	select DRIVERS_I2C_DA7219
 	select DRIVERS_SPI_ACPI
 	select DRIVERS_USB_ACPI
+	select MAINBOARD_HAS_LIBGFXINIT
 	select MAINBOARD_HAS_SPI_TPM_CR50
 
 config VARIANT_SPECIFIC_OPTIONS_SORAKA

src/mainboard/google/poppy/Makefile.inc

@@ -24,6 +24,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 ramstage-y += mainboard.c
 ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 
 smm-y += smihandler.c
 smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c

src/mainboard/google/poppy/gma-mainboard.ads

@@ -0,0 +1,31 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (Internal,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -1,5 +1,12 @@
 chip soc/intel/skylake
 
+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = "500"
+	register "gpu_pp_cycle_delay_ms"	  = "600"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"