northbridge/intel: add missing #include guards

I first found the missing of #include guards when I tried to include
both sandybridge/gma.h and sandybridge/sandybridge.h, but
sandybridge.h includes gma.h in it and gives a compile error.

Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/northbridge/intel/e7501/e7501.h

@@ -18,6 +18,9 @@
  * e7501.h: PCI configuration space for the Intel E7501 memory controller
  */
 
+#ifndef NORTHBRIDGE_INTEL_E7501_E7501_H
+#define NORTHBRIDGE_INTEL_E7501_E7501_H
+
 /************  D0:F0 ************/
 // Register offsets
 #define MAYBE_SMRBASE	0x14	/* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */
@@ -73,3 +76,5 @@
 #define NERR_GLOBAL			0x44	/* Next global error register, 32 bits */
 #define DRAM_FERR			0x80	/* DRAM first error register, 8 bits */
 #define DRAM_NERR			0x82	/* DRAM next error register, 8 bits */
+
+#endif /* NORTHBRIDGE_INTEL_E7501_E7501_H */

src/northbridge/intel/e7505/e7505.h

@@ -18,6 +18,9 @@
  * e7505.h: PCI configuration space for the Intel E7501 memory controller
  */
 
+#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
+#define NORTHBRIDGE_INTEL_E7505_E7505_H
+
 /************  D0:F0 ************/
 // Register offsets
 #define SMRBASE		0x14	/* System Memory RCOMP Base Address Register, 32 bit? */
@@ -78,3 +81,5 @@
 #define NERR_GLOBAL	0x44	/* Next global error register, 32 bits */
 #define DRAM_FERR	0x80	/* DRAM first error register, 8 bits */
 #define DRAM_NERR	0x82	/* DRAM next error register, 8 bits */
+
+#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */

src/northbridge/intel/fsp_sandybridge/chip.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H
+#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H
+
 #include <drivers/intel/gma/i915.h>
 
 /*
@@ -39,3 +42,5 @@ struct northbridge_intel_fsp_sandybridge_config {
 
 	struct i915_gpu_controller_info gfx;
 };
+
+#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H */

src/northbridge/intel/fsp_sandybridge/gma.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H
+#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H
+
 /* mailbox 0: header */
 typedef struct {
 	u8	signature[16];
@@ -161,3 +164,5 @@ typedef struct {
 } __attribute__((packed)) optionrom_vbt_t;
 
 #define VBT_SIGNATURE 0x54425624
+
+#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H */

src/northbridge/intel/haswell/chip.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H
+#define NORTHBRIDGE_INTEL_HASWELL_CHIP_H
+
 #include <drivers/intel/gma/i915.h>
 
 /*
@@ -41,3 +44,5 @@ struct northbridge_intel_haswell_config {
 };
 
 extern struct chip_operations northbridge_intel_haswell_ops;
+
+#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */

src/northbridge/intel/haswell/gma.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_HASWELL_GMA_H
+#define NORTHBRIDGE_INTEL_HASWELL_GMA_H
+
 /* mailbox 0: header */
 typedef struct {
 	u8	signature[16];
@@ -161,3 +164,5 @@ typedef struct {
 } __attribute__((packed)) optionrom_vbt_t;
 
 #define VBT_SIGNATURE 0x54425624
+
+#endif /* NORTHBRIDGE_INTEL_HASWELL_GMA_H */

src/northbridge/intel/i3100/chip.h

@@ -13,8 +13,13 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_I3100_CHIP_H
+#define NORTHBRIDGE_INTEL_I3100_CHIP_H
+
 struct northbridge_intel_i3100_config
 {
 	/* Interrupt line connect */
 	u16 intrline;
 };
+
+#endif /* NORTHBRIDGE_INTEL_I3100_CHIP_H */

src/northbridge/intel/i440bx/i440bx.h

@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H
+#define NORTHBRIDGE_INTEL_I440BX_I440BX_H
+
 /*
  * Datasheet:
  *   - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller
@@ -82,3 +85,5 @@
 #define DWTC    0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
 #define DRTC    0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
 #define BUFFC   0xf0 /* Buffer Control Register (0x0000). */
+
+#endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */

src/northbridge/intel/i82830/i82830.h

@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H
+#define NORTHBRIDGE_INTEL_I82830_I82830_H
+
 #define RRBAR   0x48 /* Register Range Base Address (0x00000000) */
 #define GCC0    0x50 /* GMCH Control #0 (0xa072) */
 #define GCC1    0x52 /* GMCH Control #1 (0x0000) */
@@ -45,3 +48,5 @@
 #define APBASE  0x10 /* Aperture Base Configuration (0x00000008) */
 #define APSIZE  0xb4 /* Apterture Size (0x00) */
 #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */
+
+#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */

src/northbridge/intel/i855/i855.h

@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_I855_I855_H
+#define NORTHBRIDGE_INTEL_I855_I855_H
+
 /* Host-Hub Interface Bridge */
 #define GMC      0x50 /* GMCH Misc. Control (0x0000) */
 #define GGC      0x52 /* GMCH Graphics Control (0x0030) */
@@ -70,3 +73,5 @@
 #define DRT_TRAS_MIN_7       (1 << 9)
 #define DRT_TRAS_MIN_6       (2 << 9)
 #define DRT_TRAS_MIN_5       (3 << 9)
+
+#endif /* NORTHBRIDGE_INTEL_I855_I855_H */

src/northbridge/intel/i945/chip.h

@@ -1,3 +1,6 @@
+#ifndef NORTHBRIDGE_INTEL_I945_CHIP_H
+#define NORTHBRIDGE_INTEL_I945_CHIP_H
+
 #include <drivers/intel/gma/i915.h>
 
 struct northbridge_intel_i945_config {
@@ -6,3 +9,5 @@ struct northbridge_intel_i945_config {
 	int gpu_lvds_use_spread_spectrum_clock;
 	struct i915_gpu_controller_info gfx;
 };
+
+#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */

src/northbridge/intel/nehalem/chip.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
+#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
+
 #include <drivers/intel/gma/i915.h>
 
 /*
@@ -39,3 +42,5 @@ struct northbridge_intel_nehalem_config {
 
 	struct i915_gpu_controller_info gfx;
 };
+
+#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */

src/northbridge/intel/pineview/chip.h

@@ -1,3 +1,6 @@
+#ifndef NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H
+#define NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H
+
 #include <drivers/intel/gma/i915.h>
 
 struct northbridge_intel_pineview_config {
@@ -7,3 +10,5 @@ struct northbridge_intel_pineview_config {
 	int gpu_lvds_use_spread_spectrum_clock;
 	struct i915_gpu_controller_info gfx;
 };
+
+#endif /* NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H */

src/northbridge/intel/sandybridge/chip.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H
+#define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H
+
 #include <drivers/intel/gma/i915.h>
 
 /*
@@ -45,3 +48,5 @@ struct northbridge_intel_sandybridge_config {
 
 	struct i915_gpu_controller_info gfx;
 };
+
+#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */

src/northbridge/intel/sandybridge/gma.h

@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H
+#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H
+
 /* mailbox 0: header */
 typedef struct {
 	u8	signature[16];
@@ -114,3 +117,5 @@ struct i915_gpu_controller_info;
 
 int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 		u32 physbase, u16 pio, u8 *mmio, u32 lfb);
+
+#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */

src/northbridge/intel/sch/nvs.h

@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef NORTHBRIDGE_INTEL_SCH_NVS_H
+#define NORTHBRIDGE_INTEL_SCH_NVS_H
+
 typedef struct {
 	u16 osys;
 	u8 smif;
@@ -100,3 +103,5 @@ typedef struct {
 	u8 idet;
 	u8 dock;
 } global_nvs_t;
+
+#endif /* NORTHBRIDGE_INTEL_SCH_NVS_H */