From d7f26b60bf899668ad5244702140e94e03bd38a1 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 28 Aug 2014 15:49:31 -0500 Subject: [PATCH] ryu: configure plld for display usage The kernel doesn't have the logic for bringing up the plld. Therefore, configure it in the firmware. The clock used is an interim value until the display controller sequencing is fully implemented. BUG=chrome-os-partner:31640 BRANCH=None TEST=Noted configured freq is close to requested. Also, no more plld errors observed from the kernel. Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f Signed-off-by: Patrick Georgi Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/214841 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9026 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/rush_ryu/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 3828a36164..79538555cc 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -50,7 +50,16 @@ static const struct funit_cfg funits[] = { static void mainboard_init(device_t dev) { + /* PLLD should be 2 * pixel clock (301620khz). */ + const uint32_t req_disp_clk = 301620 * 1000 * 2; + uint32_t disp_clk; + soc_configure_funits(funits, ARRAY_SIZE(funits)); + disp_clk = clock_display(req_disp_clk); + + if (disp_clk != req_disp_clk) + printk(BIOS_DEBUG, "display clock: %u vs %u (r)\n", disp_clk, + req_disp_clk); } static void mainboard_enable(device_t dev)