cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target

Use the newly introduced 'all_x86' make target to add the compilation
unit to all stages that run on the x86 cores, but not to verstage on
PSP.

TEST=Timeless build for Mandolin results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74152
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-04-01 01:51:06 +02:00
parent f008e0af16
commit d801d00f23
3 changed files with 4 additions and 20 deletions

View File

@ -4,14 +4,6 @@ bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
bootblock-y += boot_cpu.c
verstage_x86-y += boot_cpu.c
romstage-y += boot_cpu.c
ramstage-y += boot_cpu.c
postcar-y += boot_cpu.c
bootblock-y += lapic.c
verstage_x86-y += lapic.c
romstage-y += lapic.c
ramstage-y += lapic.c
postcar-y += lapic.c
all_x86-y += boot_cpu.c
all_x86-y += lapic.c

View File

@ -1,6 +1,2 @@
bootblock-y += pgtbl.c
verstage_x86-y += pgtbl.c
romstage-y += pgtbl.c
postcar-y += pgtbl.c
ramstage-y += pgtbl.c
all_x86-y += pgtbl.c
smm-y += pgtbl.c

View File

@ -1,6 +1,2 @@
bootblock-y += delay_tsc.c
ramstage-y += delay_tsc.c
romstage-y += delay_tsc.c
verstage_x86-y += delay_tsc.c
postcar-y += delay_tsc.c
all_x86-y += delay_tsc.c
smm-y += delay_tsc.c