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slippy: Clean up for easier porting 

Minor tweaks to variable names in the slippy mainboard
that make it easier to base a new board from without
as much renaming.

Also properly set up the thermal variables for the
thermal zone that is defined in ACPI instead of using
the generic setup from WTM2.

Change-Id: I752c1a50bfdc06b6ddad95bd1331c6870b9f9df2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56328
Reviewed-on: http://review.coreboot.org/4183
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Duncan Laurie 2013-05-22 16:13:49 -07:00 committed by Alexandru Gagniuc
parent cfe0235c6f
commit d80cd2ad80
7 changed files with 38 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/mainboard/google/slippy/acpi_tables.c
View File

@ -43,29 +43,18 @@ unsigned long acpi_create_slic(unsigned long current);
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->f4of = FAN4_THRESHOLD_OFF;
gnvs->f4on = FAN4_THRESHOLD_ON;
gnvs->f4pw = FAN4_PWM;
gnvs->tmps = CTDP_SENSOR_ID;
gnvs->f3of = FAN3_THRESHOLD_OFF;
gnvs->f3on = FAN3_THRESHOLD_ON;
gnvs->f3pw = FAN3_PWM;
gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;
gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON;
gnvs->f2of = FAN2_THRESHOLD_OFF;
gnvs->f2on = FAN2_THRESHOLD_ON;
gnvs->f2pw = FAN2_PWM;
gnvs->f1of = FAN1_THRESHOLD_OFF;
gnvs->f1on = FAN1_THRESHOLD_ON;
gnvs->f1pw = FAN1_PWM;
gnvs->f0of = FAN0_THRESHOLD_OFF;
gnvs->f0on = FAN0_THRESHOLD_ON;
gnvs->f0pw = FAN0_PWM;
gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF;
gnvs->f0on = CTDP_DOWN_THRESHOLD_ON;
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;
gnvs->flvl = 1;
}
static void acpi_create_gnvs(global_nvs_t *gnvs)

14
src/mainboard/google/slippy/ec.c
View File

@ -24,25 +24,25 @@
#include <ec/google/chromeec/ec.h>
#include "ec.h"
void slippy_ec_init(void)
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "slippy_ec_init\n");
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
/* Restore SCI event mask on resume. */
if (acpi_slp_type == 3) {
google_chromeec_log_events(SLIPPY_EC_LOG_EVENTS |
SLIPPY_EC_S3_WAKE_EVENTS);
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(SLIPPY_EC_SCI_EVENTS);
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(SLIPPY_EC_LOG_EVENTS |
SLIPPY_EC_S5_WAKE_EVENTS);
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */

18
src/mainboard/google/slippy/ec.h
View File

@ -17,15 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SLIPPY_EC_H
#define SLIPPY_EC_H
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <ec/google/chromeec/ec_commands.h>
#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
#define SLIPPY_EC_SCI_EVENTS \
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
@ -37,26 +37,26 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
#define SLIPPY_EC_SMI_EVENTS \
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define SLIPPY_EC_S5_WAKE_EVENTS \
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */
#define SLIPPY_EC_S3_WAKE_EVENTS \
(SLIPPY_EC_S5_WAKE_EVENTS |\
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
/* Log EC wake events plus EC shutdown events */
#define SLIPPY_EC_LOG_EVENTS \
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
#ifndef __ACPI__
extern void slippy_ec_init(void);
extern void mainboard_ec_init(void);
#endif
#endif

2
src/mainboard/google/slippy/gpio.h
View File

@ -20,7 +20,7 @@
#ifndef SLIPPY_GPIO_H
#define SLIPPY_GPIO_H
#include "southbridge/intel/lynxpoint/lp_gpio.h"
struct pch_lp_gpio_map;
const struct pch_lp_gpio_map mainboard_gpio_map[] = {
LP_GPIO_UNUSED, /* 0: UNUSED */

2
src/mainboard/google/slippy/mainboard.c
View File

@ -142,7 +142,7 @@ static void verb_setup(void)
static void mainboard_init(device_t dev)
{
slippy_ec_init();
mainboard_ec_init();
}
// mainboard_enable is executed as first thing after

6
src/mainboard/google/slippy/smihandler.c
View File

@ -117,7 +117,7 @@ void mainboard_smi_sleep(u8 slp_typ)
while (google_chromeec_get_event() != 0);
/* Enable wake events */
google_chromeec_set_wake_mask(SLIPPY_EC_S3_WAKE_EVENTS);
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
}
#define APMC_FINALIZE 0xcb
@ -144,13 +144,13 @@ int mainboard_smi_apmc(u8 apmc)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_sci_mask(SLIPPY_EC_SCI_EVENTS);
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(SLIPPY_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
break;
}
return 0;

34
src/mainboard/google/slippy/thermal.h
View File

@ -20,36 +20,22 @@
#ifndef THERMAL_H
#define THERMAL_H
/* Fan is OFF */
#define FAN4_THRESHOLD_OFF 0
#define FAN4_THRESHOLD_ON 0
#define FAN4_PWM 0x00
/* Config TDP Sensor ID */
#define CTDP_SENSOR_ID 1 /* PECI */
/* Fan is at LOW speed */
#define FAN3_THRESHOLD_OFF 48
#define FAN3_THRESHOLD_ON 55
#define FAN3_PWM 0x40
/* Config TDP Nominal */
#define CTDP_NOMINAL_THRESHOLD_OFF 0
#define CTDP_NOMINAL_THRESHOLD_ON 0
/* Fan is at MEDIUM speed */
#define FAN2_THRESHOLD_OFF 52
#define FAN2_THRESHOLD_ON 64
#define FAN2_PWM 0x80
/* Fan is at HIGH speed */
#define FAN1_THRESHOLD_OFF 60
#define FAN1_THRESHOLD_ON 68
#define FAN1_PWM 0xb0
/* Fan is at FULL speed */
#define FAN0_THRESHOLD_OFF 66
#define FAN0_THRESHOLD_ON 78
#define FAN0_PWM 0xff
/* Config TDP Down */
#define CTDP_DOWN_THRESHOLD_OFF 80
#define CTDP_DOWN_THRESHOLD_ON 90
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 100
#define CRITICAL_TEMPERATURE 104
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
#define PASSIVE_TEMPERATURE 100
/* Tj_max value for calculating PECI CPU temperature */
#define MAX_TEMPERATURE 105