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mb/google/volteer: Improve Eldrid Port 1 USB2 Eye Diagram 

In order to pass DB type-C USB2 eye diagram, DB USB2 PHY register needs 
to be overridden.

port#1
PortUsb20Enable=1
Usb2PhyPetxiset=7
Usb2PhyTxiset=7
Usb2PhyPredeemp=3
Usb2PhyPehalfbit=0

BUG=b:169105751
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: If076c644783fa2992ac062d6469f9c49e6d5ff24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
nick_xr_chen 2020-09-22 10:56:43 +08:00 committed by Patrick Georgi
parent 1bdbcd7510
commit d8279fdb6d
1 changed files with 9 additions and 0 deletions
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9
src/mainboard/google/volteer/variants/eldrid/overridetree.cb
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@ -48,6 +48,15 @@ chip soc/intel/tigerlake
},
},
}"
#These settings improve the USB2 Port1 eye diagram
register "usb2_ports[4]" = "{
.enable = 1,
.tx_bias = 7,
.tx_emp_enable = 7,
.pre_emp_bias = 3,
.pre_emp_bit = 0,
}"
device domain 0 on
device pci 04.0 off end
device pci 15.0 on