soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to table

GPIO bank 3 isn't used in coreboot, but the existence is documented in
both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and
for those two SoCs all 4 banks are covered by the corresponding
Memory32Fixed region in the DSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/include/amdblocks/acpimmio_map.h

@@ -72,6 +72,8 @@
  * +---------------------------------------------------------------------------+
  * |0x1700   GPIO configuration registers bank 2 (following bank 1)            |
  * +---------------------------------------------------------------------------+
+ * |0x1800   GPIO configuration registers bank 3 (following bank 2)            |
+ * +---------------------------------------------------------------------------+
  * |0x1c00   xHCI Power Management registers                                   |
  * +---------------------------------------------------------------------------+
  * |0x1d00   Wake device (AC DC timer)                                         |