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This goes a surprisingly long way to building the epia-n. It also has 

important corrections to the Kconfig and Makefile.inc that were there. I
would like to go ahead and get this in, because I don't want anyone to
continue using what is in the upstream tree as it now exists.
I also tested old-style build with this and it did not break anything.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2009-08-20 18:05:31 +00:00
parent b203c2f95e
commit d82e12858f
11 changed files with 265 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/via/Makefile.inc
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@ -1,2 +1,3 @@
#subdirs-y += model_c7
subdirs-y += model_c7
subdirs-$(CONFIG_CPU_VIA_C7) += model_c7
subdirs-$(CONFIG_CPU_VIA_C3) += model_c3

3
src/cpu/via/model_c3/Kconfig Normal file
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@ -0,0 +1,3 @@
config CPU_VIA_C3
bool
default n

11
src/cpu/via/model_c3/Makefile.inc Normal file
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@ -0,0 +1,11 @@
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/fpu
subdirs-y += ../../x86/mmx
subdirs-y += ../../x86/sse
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../../intel/microcode
obj-y += model_c3_init.o

20
src/cpu/via/model_c7/Makefile.inc
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@ -1,13 +1,11 @@
ifeq ($(CONFIG_CPU_VIA_C7),y)
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/fpu
subdirs-y += ../../x86/mmx
subdirs-y += ../../x86/sse
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../../intel/microcode
endif
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/fpu
subdirs-y += ../../x86/mmx
subdirs-y += ../../x86/sse
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../../intel/microcode
obj-y += model_c7_init.o

33
src/mainboard/via/Kconfig
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@ -2,36 +2,9 @@ choice
prompt "Mainboard model"
depends on VENDOR_VIA
config BOARD_VIA_VT8454C
bool "vt8454c"
select ARCH_X86
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CX700
# select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_VIA_VT1211
select PIRQ_TABLE
# select MMCONF_SUPPORT
select USE_PRINTK_IN_CAR
help
Kontron 986LCD-M Series mainboards
source "src/mainboard/via/vt8454c/Kconfig"
source "src/mainboard/via/epia-n/Kconfig"
endchoice
config MAINBOARD_DIR
string
default via/vt8454c
depends on BOARD_VIA_VT8454C
config DCACHE_RAM_BASE
hex
default 0xffef0000
depends on BOARD_VIA_VT8454C
config DCACHE_RAM_SIZE
hex
default 0x8000
depends on BOARD_VIA_VT8454C
config MAINBOARD_PART_NUMBER
string
default "VT8454C"
depends on BOARD_VIA_VT8454C

37
src/mainboard/via/epia-n/Kconfig Normal file
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@ -0,0 +1,37 @@
config BOARD_VIA_EPIA_N
bool "via epia-n"
select ARCH_X86
select CPU_VIA_C3
select NORTHBRIDGE_VIA_CN400
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_WINBOND_W83697HF
select PIRQ_TABLE
select USE_PRINTK_IN_CAR
help
VIA Epia-n mainboards
config MAINBOARD_DIR
string
default via/epia-n
depends on BOARD_VIA_EPIA_N
#config DCACHE_RAM_BASE
# hex
# default 0xffef0000
# depends on BOARD_VIA_EPIA_N
#
#config DCACHE_RAM_SIZE
# hex
# default 0x8000
# depends on BOARD_VIA_EPIA_N
config MAINBOARD_PART_NUMBER
string
default "EPIA_N"
depends on BOARD_VIA_EPIA_N
config VIDEO_MB
int
default 32
depends on BOARD_VIA_EPIA_N

64
src/mainboard/via/epia-n/Makefile.inc Normal file
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@ -0,0 +1,64 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 VIA Technologies, Inc.
## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
initobj-y += crt0.o
obj-y += mainboard.o
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_HAVE_MP_TABLE) += object mptable.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
ldscript-y += ../../../../src/arch/i386/lib/id.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
crt0-y += auto.inc
crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
ifdef POST_EVALUATION
MAINBOARD_OPTIONS=\
-DCONFIG_USE_PRINTK_IN_CAR=1 \
-DCONFIG_HAVE_HIGH_TABLES=1
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
mv dsdt.hex $@
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

101
src/mainboard/via/epia-n/devicetree.cb Normal file
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@ -0,0 +1,101 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 VIA Technologies, Inc.
## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
chip northbridge/via/cn400 # Northbridge
device apic_cluster 0 on # APIC cluster
chip cpu/via/model_c3 # VIA C3
device apic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
device pci 0.0 on end # AGP Bridge
device pci 0.1 on end # Error Reporting
device pci 0.2 on end # Host Bus Control
device pci 0.3 on end # Memory Controller
device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller
device pci 1.0 on end # PCI Bridge
chip southbridge/via/vt8237r # Southbridge
# Enable both IDE channels.
register "ide0_enable" = "1"
register "ide1_enable" = "1"
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
device pci f.0 on end # IDE/SATA
device pci f.1 on end # IDE
register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97
register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating
device pci 10.0 on end # OHCI
device pci 10.1 on end # OHCI
device pci 10.2 on end # OHCI
device pci 10.3 on end # OHCI
device pci 10.4 on end # EHCI
device pci 10.5 off end # USB Direct
device pci 11.0 on # Southbridge LPC
chip superio/winbond/w83697hf # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.6 off # IR Port
io 0x60 = 0x000
end
device pnp 2e.7 off # GPIO 1
io 0x60 = 0x201 # 0x201
end
device pnp 2e.8 off # GPIO 5
io 0x60 = 0x330 # 0x330
end
device pnp 2e.9 off # GPIO 2, 3,and 4
io 0x60 = 0x000 #
end
device pnp 2e.a off # ACPI
io 0x60 = 0x000 #
end
device pnp 2e.b on # HWM
io 0x60 = 0x290
irq 0x70 = 0
end
end
end
device pci 11.5 off end # AC'97 audio
device pci 11.6 off end # AC'97 Modem
device pci 12.0 on end # Ethernet
end
end
end

32
src/mainboard/via/vt8454c/Kconfig Normal file
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@ -0,0 +1,32 @@
config BOARD_VIA_VT8454C
bool "vt8454c"
select ARCH_X86
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CX700
# select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_VIA_VT1211
select PIRQ_TABLE
# select MMCONF_SUPPORT
select USE_PRINTK_IN_CAR
help
Kontron 986LCD-M Series mainboards
config MAINBOARD_DIR
string
default via/vt8454c
depends on BOARD_VIA_VT8454C
config DCACHE_RAM_BASE
hex
default 0xffef0000
depends on BOARD_VIA_VT8454C
config DCACHE_RAM_SIZE
hex
default 0x8000
depends on BOARD_VIA_VT8454C
config MAINBOARD_PART_NUMBER
string
default "VT8454C"
depends on BOARD_VIA_VT8454C

1
src/northbridge/via/Kconfig
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@ -1,5 +1,6 @@
#source src/northbridge/via/cn700/Kconfig
source src/northbridge/via/cx700/Kconfig
source src/northbridge/via/cn400/Kconfig
#source src/northbridge/via/vt8601/Kconfig
#source src/northbridge/via/vt8623/Kconfig
#source src/northbridge/via/vx800/Kconfig

2
src/northbridge/via/cn400/cn400.h
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@ -19,7 +19,7 @@
*/
#ifndef __ROMCC__
static void cn400_noop()
static void cn400_noop(void)
{
}
#endif