AMD Norwich: minor cosmetic fixes and drop dead code (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
4aae668fed
commit
d83f79f3b8
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@ -40,7 +40,7 @@
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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}
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@ -50,6 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#define PLLMSRlo 0x02000030
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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#include "northbridge/amd/lx/raminit.h"
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#include "northbridge/amd/lx/pll_reset.c"
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#include "northbridge/amd/lx/raminit.c"
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@ -60,6 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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static void msr_init(void)
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{
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msr_t msr;
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/* Setup access to the cache for under 1MB. */
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msr.hi = 0x24fffc02;
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msr.lo = 0x1000A000; /* 0-A0000 write back */
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@ -87,12 +89,11 @@ static void msr_init(void)
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msr.hi = 0x20000000;
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msr.lo = 0x80fffe0;
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wrmsr(MSR_GLIU1 + 0x21, msr);
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}
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup */
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/* Early mainboard specific GPIO setup. */
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}
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void cache_as_ram_main(void)
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@ -108,9 +109,8 @@ void cache_as_ram_main(void)
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cs5536_early_setup();
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536
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/* Note: must do this AFTER the early_setup! It is counting on some early
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* MSR setup for CS5536.
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*/
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/* cs5536_disable_internal_uart disable them for now, set them up later... */
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cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
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@ -124,9 +124,9 @@ void cache_as_ram_main(void)
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sdram_initialize(1, memctrl);
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/* Check all of memory */
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/* Check memory. */
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/* ram_check(0x00000000, 640 * 1024); */
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/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
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/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
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return;
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}
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@ -8,24 +8,5 @@
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static unsigned long main(unsigned long bist)
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{
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#if 0
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/* This is the primary cpu how should I boot? */
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if (do_normal_boot()) {
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goto normal_image;
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} else {
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goto fallback_image;
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}
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normal_image:
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asm volatile ("jmp __normal_image": /* outputs */
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:"a" (bist) /* inputs */
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: /* clobbers */
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);
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cpu_reset:
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asm volatile ("jmp __cpu_reset": /* outputs */
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:"a" (bist) /* inputs */
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: /* clobbers */
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);
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fallback_image:
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#endif
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return bist;
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}
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@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirtable_end = copy_pirq_routing_table(addr);
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/* Set up chipset IRQ steering */
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/* Set up chipset IRQ steering. */
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pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
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printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
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@ -86,20 +86,23 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq_tbl = (struct irq_routing_table *)(addr);
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num_entries = (pirq_tbl->size - 32) / 16;
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/* Set PCI IRQs */
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/* Set PCI IRQs. */
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for (i = 0; i < num_entries; i++) {
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printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
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pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++) {
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printk_debug("INT: %c bitmap: %x ", 'A' + j,
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pirq_tbl->slots[i].irq[j].bitmap);
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for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* finds lsb in bitmap to IRQ# */
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for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
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pirq[j] = k;
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printk_debug("PIRQ: %d\n", k);
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}
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pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
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/* Bus, device, slots IRQs for {A,B,C,D}. */
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pci_assign_irqs(pirq_tbl->slots[i].bus,
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pirq_tbl->slots[i].devfn >> 3, pirq);
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}
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/* put the PIR table in memory and checksum */
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/* Put the PIR table in memory and checksum. */
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return pirtable_end;
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}
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@ -26,7 +26,9 @@
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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#include "chip.h"
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/* Print the platform configuration - do before PCI init or it will not work right */
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/* Print the platform configuration - do before PCI init or it will not
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* work right.
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*/
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void print_conf(void)
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{
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#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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@ -34,61 +36,49 @@ void print_conf(void)
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unsigned long iol;
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msr_t msr;
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int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
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CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
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CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF,
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CPU_RCONF_E0_FF,
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CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
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int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
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CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
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CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
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GLCP_DELAY_CONTROLS, GL_END
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};
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int gliu0_msr_defs[] =
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{ MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4,
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MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
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int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
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MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
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GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
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GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
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MSR_GLIU0_SHADOW,
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GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
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GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3,
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GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
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MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
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GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
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GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
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GLIU0_GLD_MSR_COH, GL_END
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};
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int gliu1_msr_defs[] =
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{ MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3,
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MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
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MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9,
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MSR_GLIU1_BASE10,
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GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3,
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MSR_GLIU1_SHADOW,
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GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
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GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
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int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
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MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
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MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
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MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
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GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
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GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
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GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
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GLIU1_GLD_MSR_COH, GL_END
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};
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int rconf_msr[] =
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{ CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
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CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
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int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
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CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
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};
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int cs5536_msr[] =
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{ MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO,
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MDD_PIN_OPT,
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MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
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int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
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MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
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MDD_IRQM_PRIM, GL_END
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};
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int pci_msr[] =
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{ GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF,
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GLPCI_E0_FF,
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GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR,
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GLPCI_SPARE,
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GL_END
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int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
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GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
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GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
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};
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int dma_msr[] =
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{ MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3,
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MDD_DMA_SHAD4,
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MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
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MDD_DMA_SHAD9, GL_END
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int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
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MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
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MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
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};
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printk_debug("---------- CPU ------------\n");
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@ -1,12 +1,12 @@
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# Config file for the AMD Geode LX/5536 Norwich Platform
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# Config file for the AMD Geode LX/5536 Norwich Platform.
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target norwich
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mainboard amd/norwich
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#HACK to get the right tsc support
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# HACK to get the right TSC support.
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option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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# leave 36k for vsa
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# Leave 36k for VSA.
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option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
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option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
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