nb/intel/gm45: Tidy up comments and cosmetics
Use C-style comments, drop an unneeded newline, add missing commas for consistency and relocate a comment to match the code. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
7c71f7d15b
commit
d85d7e2329
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@ -9,205 +9,205 @@ Name(_BBN, 0)
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Device (MCHC)
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{
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Name(_ADR, 0x00000000) // 0:0.0
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Name(_ADR, 0x00000000) /* 0:0.0 */
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OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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Offset (0x40), // EPBAR
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EPEN, 1, // Enable
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, 11, //
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EPBR, 24, // EPBAR
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Offset (0x40), /* EPBAR */
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EPEN, 1, /* Enable */
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, 11,
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EPBR, 24, /* EPBAR */
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Offset (0x48), // MCHBAR
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MHEN, 1, // Enable
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, 13, //
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MHBR, 22, // MCHBAR
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Offset (0x48), /* MCHBAR */
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MHEN, 1, /* Enable */
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, 13,
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MHBR, 22, /* MCHBAR */
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Offset (0x60), // PCIe BAR
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PXEN, 1, // Enable
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PXSZ, 2, // BAR size
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, 23, //
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PXBR, 10, // PCIe BAR
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Offset (0x60), /* PCIec BAR */
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PXEN, 1, /* Enable */
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PXSZ, 2, /* BAR size */
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, 23,
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PXBR, 10, /* PCIe BAR */
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Offset (0x68), // DMIBAR
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DMEN, 1, // Enable
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, 11, //
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DMBR, 24, // DMIBAR
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Offset (0x68), /* DMIBAR */
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DMEN, 1, /* Enable */
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, 11,
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DMBR, 24, /* DMIBAR */
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// ...
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/* ... */
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Offset (0x90), // PAM0
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Offset (0x90), /* PAM0 */
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, 4,
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PM0H, 2,
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, 2,
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Offset (0x91), // PAM1
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Offset (0x91), /* PAM1 */
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PM1L, 2,
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, 2,
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PM1H, 2,
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, 2,
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Offset (0x92), // PAM2
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Offset (0x92), /* PAM2 */
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PM2L, 2,
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, 2,
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PM2H, 2,
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, 2,
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Offset (0x93), // PAM3
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Offset (0x93), /* PAM3 */
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PM3L, 2,
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, 2,
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PM3H, 2,
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, 2,
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Offset (0x94), // PAM4
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Offset (0x94), /* PAM4 */
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PM4L, 2,
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, 2,
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PM4H, 2,
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, 2,
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Offset (0x95), // PAM5
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Offset (0x95), /* PAM5 */
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PM5L, 2,
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, 2,
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PM5H, 2,
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, 2,
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Offset (0x96), // PAM6
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Offset (0x96), /* PAM6 */
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PM6L, 2,
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, 2,
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PM6H, 2,
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, 2,
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Offset (0xa0), // Top of Used Memory
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Offset (0xa0), /* Top of Memory */
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TOM, 8,
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Offset (0xb0), // Top of Low Used Memory
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Offset (0xb0), /* Top of Low Used Memory */
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, 4,
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TLUD, 12,
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}
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}
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// Current Resource Settings
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Name (MCRS, ResourceTemplate()
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{
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// Bus Numbers
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/* Bus Numbers */
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
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// IO Region 0
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/* IO Region 0 */
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
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// PCI Config Space
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/* PCI Config Space */
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Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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// IO Region 1
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/* IO Region 1 */
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
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// VGA memory (0xa0000-0xbffff)
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/* VGA memory (0xa0000-0xbffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000,,, ASEG)
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// OPROM reserved (0xc0000-0xc3fff)
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/* OPROM reserved (0xc0000-0xc3fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000,,, OPR0)
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// OPROM reserved (0xc4000-0xc7fff)
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/* OPROM reserved (0xc4000-0xc7fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000,,, OPR1)
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// OPROM reserved (0xc8000-0xcbfff)
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/* OPROM reserved (0xc8000-0xcbfff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000,,, OPR2)
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// OPROM reserved (0xcc000-0xcffff)
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/* OPROM reserved (0xcc000-0xcffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000,,, OPR3)
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// OPROM reserved (0xd0000-0xd3fff)
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/* OPROM reserved (0xd0000-0xd3fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000,,, OPR4)
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// OPROM reserved (0xd4000-0xd7fff)
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/* OPROM reserved (0xd4000-0xd7fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000,,, OPR5)
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// OPROM reserved (0xd8000-0xdbfff)
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/* OPROM reserved (0xd8000-0xdbfff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000,,, OPR6)
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// OPROM reserved (0xdc000-0xdffff)
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/* OPROM reserved (0xdc000-0xdffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000,,, OPR7)
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// BIOS Extension (0xe0000-0xe3fff)
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/* BIOS Extension (0xe0000-0xe3fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000,,, ESG0)
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// BIOS Extension (0xe4000-0xe7fff)
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/* BIOS Extension (0xe4000-0xe7fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000,,, ESG1)
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// BIOS Extension (0xe8000-0xebfff)
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/* BIOS Extension (0xe8000-0xebfff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000,,, ESG2)
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// BIOS Extension (0xec000-0xeffff)
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/* BIOS Extension (0xec000-0xeffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000,,, ESG3)
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// System BIOS (0xf0000-0xfffff)
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/* System BIOS (0xf0000-0xfffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000,,, FSEG)
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// PCI Memory Region (Top of memory-0xfebfffff)
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/* PCI Memory Region (Top of memory-0xfebfffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
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IO_APIC_ADDR,,, PM01)
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// TPM Area (0xfed40000-0xfed44fff)
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/* TPM Area (0xfed40000-0xfed44fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
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0x00005000,,, TPMR)
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})
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/* Current Resource Settings */
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Method (_CRS, 0, Serialized)
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{
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// Find PCI resource area in MCRS
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/* Find PCI resource area in MCRS */
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CreateDwordField(MCRS, ^PM01._MIN, PMIN)
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CreateDwordField(MCRS, ^PM01._MAX, PMAX)
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CreateDwordField(MCRS, ^PM01._LEN, PLEN)
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// Fix up PCI memory region:
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// Enter actual TOLUD. The TOLUD register contains bits 20-31 of
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// the top of memory address.
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/*
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* Fix up PCI memory region:
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* Enter actual TOLUD. The TOLUD register contains bits 20-31 of
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* the top of memory address.
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*/
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ShiftLeft (^MCHC.TLUD, 20, PMIN)
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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@ -12,16 +12,15 @@ Device (PEGP)
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Package() { 0x0000ffff, 0, 0, 16 },
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Package() { 0x0000ffff, 1, 0, 17 },
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Package() { 0x0000ffff, 2, 0, 18 },
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Package() { 0x0000ffff, 3, 0, 19 }
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Package() { 0x0000ffff, 3, 0, 19 },
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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})
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}
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}
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}
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