GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: Remove duplicate CPUID entry 

This patch removes duplicate CPUID entry between KBL and CFL.
CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL
CPUID (0x806EA) for CFL-D0.

TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with
CPUID 0x806EA.

Change-Id: I078dd7860891896b512967dc8dec5dd94d069193
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Subrata Banik 2020-02-03 10:51:01 +05:30 committed by Patrick Georgi
parent 6ec322ec7c
commit d8663e0fc6
3 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/cannonlake/bootblock/report_platform.c
View File

@ -37,7 +37,7 @@ static struct {
{ CPUID_CANNONLAKE_B0, "Cannonlake B0" }, { CPUID_CANNONLAKE_B0, "Cannonlake B0" },
{ CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_C0, "Cannonlake C0" },
{ CPUID_CANNONLAKE_D0, "Cannonlake D0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" },
{ CPUID_COFFEELAKE_D0, "Coffeelake D0" }, { CPUID_KABYLAKE_Y0, "Coffeelake D0" },
{ CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" },
{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" },
{ CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },

1
src/soc/intel/common/block/cpu/mp_init.c
View File

@ -75,7 +75,6 @@ static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 },
{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 },
{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 },
{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 },
{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 },
{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 },
{ X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 },

1
src/soc/intel/common/block/include/intelblocks/mp_init.h
View File

@ -40,7 +40,6 @@
#define CPUID_GLK_R0 0x706a8 #define CPUID_GLK_R0 0x706a8
#define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_V0 0x806ec
#define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_WHISKEYLAKE_W0 0x806eb
#define CPUID_COFFEELAKE_D0 0x806ea
#define CPUID_COFFEELAKE_U0 0x906ea #define CPUID_COFFEELAKE_U0 0x906ea
#define CPUID_COFFEELAKE_B0 0x906eb #define CPUID_COFFEELAKE_B0 0x906eb
#define CPUID_COFFEELAKE_P0 0x906ec #define CPUID_COFFEELAKE_P0 0x906ec