soc/intel/common/block: Add PAM locking function
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit instead of the FSP, therefore add a function in the common code to do this. Source: ADL & TGL FSP integration guides Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -79,6 +79,9 @@ uintptr_t sa_get_tseg_base(void);
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size_t sa_get_tseg_size(void);
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/* Fill MMIO resource above 4GB into GNVS */
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void sa_fill_gnvs(struct global_nvs *gnvs);
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/* API to lock PAM registers */
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void sa_lock_pam(void);
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/*
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* SoC overrides
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*
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@ -306,6 +306,15 @@ void enable_power_aware_intr(void)
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MCHBAR8(MCH_PAIR) = pair;
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}
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void sa_lock_pam(void)
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{
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const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
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if (!dev)
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return;
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pci_or_config8(dev, PAM0, PAM_LOCK);
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}
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static struct device_operations systemagent_ops = {
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.read_resources = systemagent_read_resources,
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.set_resources = pci_dev_set_resources,
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@ -35,6 +35,9 @@
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#define PAM5 0x85
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#define PAM6 0x86
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/* PAM0 contains the lock bit */
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#define PAM_LOCK (1 << 0)
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/* Device 0:0.0 MMIO space */
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#define MCH_PAIR 0x5418
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