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mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller 

Restrict ASPM to L1 for SD controller to avoid AERs.

BUG=b:288830220
TEST=No PCIE AER on SD controller on Screebo.

w/o this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
  LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
          ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # lspci -s 02:00.0 -vvv | grep -i aspm
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
          ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
  LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-

~ # dmesg | grep -i -e "pci.*error"
[    0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[    0.735258] rtsx_pci 0000:02:00.0:   device [10ec:522a] error status/mask=00001000/00006000
[    0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[    1.548894] rtsx_pci 0000:02:00.0:   device [10ec:522a] error status/mask=00001000/00006000
[    1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0
```

w/ this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
  LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
          ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # lspci -s 02:00.0 -vvv | grep -i aspm
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
          ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # dmesg | grep -i -e "pci.*error"

```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kapil Porwal 2023-07-31 12:20:31 +00:00 committed by Jakub Czapiga
parent b2e7fa515d
commit d88039cbfe
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/google/rex/variants/screebo/overridetree.cb
View File

@ -238,6 +238,7 @@ chip soc/intel/meteorlake
.clk_src = 7, .clk_src = 7,
.clk_req = 7, .clk_req = 7,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1,
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"