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soc/amd/cezanne: Add support for C-state 3 

These values match the majolica UEFI firmware.

BUG=b:185787242, b:178728116, b:185921043

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If107c7e836942eeba734c1634fa7f8555c3018b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Raul E Rangel 2021-04-19 17:00:58 -06:00 committed by Raul Rangel
parent d77b97dc9a
commit d8956f7994
1 changed files with 13 additions and 0 deletions
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13
src/soc/amd/cezanne/acpi.c
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@ -304,6 +304,19 @@ void generate_cpu_entries(const struct device *device)
.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
},
},
[2] = {
.ctype = 3,
.latency = 350,
.power = 0,
.resource = {
.space_id = ACPI_ADDRESS_SPACE_IO,
.bit_width = 8,
.bit_offset = 0,
.addrl = cstate_base_address + 2,
.addrh = 0,
.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS,
},
},
};
threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK)