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soc/intel/jasperlake: add processor power limits control support 

Add processor power limits control support to configure values for
jasperlake soc based platforms.

BRANCH=None
BUG=None
TEST=Built for dedede system

Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar 2020-05-26 19:59:45 +05:30 committed by Patrick Georgi
parent 5a082825aa
commit d8b4ea992b
1 changed files with 11 additions and 0 deletions
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11
src/soc/intel/jasperlake/systemagent.c
View File

@ -1,10 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <delay.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/power_limit.h>
#include <soc/iomap.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
/*
@ -43,9 +46,17 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
*/
void soc_systemagent_init(struct device *dev)
{
struct soc_power_limits_config *soc_config;
config_t *config;
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
/* Enable BIOS Reset CPL */
enable_bios_reset_cpl();
mdelay(1);
config = config_of_soc();
soc_config = &config->power_limits_config;
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
}