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Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. 

The MTRR check for WB TOM2 setting was only checking revF, not extended family
revisions. All families above revf indicate 0xf in the family field and have
additional bits in the extended family field.

Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones 2012-01-30 19:30:45 -07:00
parent dc0bdbab2d
commit d8d8c63cf7
1 changed files with 3 additions and 2 deletions
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5
src/cpu/amd/mtrr/amd_mtrr.c
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@ -114,12 +114,13 @@ void amd_setup_mtrrs(void)
msr_t msr, sys_cfg; msr_t msr, sys_cfg;
// Test if this CPU is a Fam 0Fh rev. F or later // Test if this CPU is a Fam 0Fh rev. F or later
const int cpu_id = cpuid_eax(0x80000001); const int cpu_id = cpuid_eax(0x80000001);
printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
const int has_tom2wb = const int has_tom2wb =
(((cpu_id>>8 )&0xf) > 0xf) || // Family > 0F (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0
((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
(((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables
if(has_tom2wb) if(has_tom2wb)
printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB\n"); printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
/* Enable the access to AMD RdDram and WrDram extension bits */ /* Enable the access to AMD RdDram and WrDram extension bits */
disable_cache(); disable_cache();