driver/intel/fsp1_1: Fix boot failure for non-verstage case
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -28,7 +28,6 @@ romstage-y += fsp_util.c
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romstage-y += hob.c
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romstage-y += raminit.c
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romstage-y += romstage.c
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romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
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romstage-y += stack.c
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romstage-y += stage_cache.c
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romstage-$(CONFIG_MMA) += mma_core.c
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@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
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}
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/* Entry point taken when romstage is called after a separate verstage. */
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asmlinkage void *romstage_after_verstage(void)
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asmlinkage void *romstage_c_entry(void)
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{
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/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
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* is still enabled. We can directly access work buffer here. */
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@ -32,7 +32,7 @@ struct cache_as_ram_params {
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/* Entry points from the cache-as-ram assembly code. */
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asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
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asmlinkage void after_cache_as_ram(void *chipset_context);
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asmlinkage void *romstage_after_verstage(void);
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asmlinkage void *romstage_c_entry(void);
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/* Per stage calls from the above two functions. The void * return from
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* cache_as_ram_stage_main() is the stack pointer to use in RAM after
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* exiting cache-as-ram mode. */
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@ -1,5 +1,6 @@
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verstage-y += power_state.c
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romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S
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romstage-y += pmc.c
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romstage-y += power_state.c
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@ -13,13 +13,15 @@
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* GNU General Public License for more details.
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*/
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#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
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/* I/O delay between post codes on failure */
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#define LHLT_DELAY 0x50000
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.text
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.global car_stage_entry
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car_stage_entry:
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call romstage_after_verstage
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#include "after_raminit.S"
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call romstage_c_entry
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#include "src/drivers/intel/fsp1_1/after_raminit.S"
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movb $0x69, %ah
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jmp .Lhlt
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