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mb/intel/saddlebrook/devicetree.cb: Use PCH_IRQ* macros 

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I6375f97bc2a30beba5882792328f26e0675621cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43867
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-25 14:57:06 +02:00
parent a7d9266832
commit d8f4436005
1 changed files with 8 additions and 8 deletions
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16
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -175,14 +175,14 @@ chip soc/intel/skylake
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0a"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x0b"
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
register "pirqc_routing" = "PCH_IRQ11"
register "pirqd_routing" = "PCH_IRQ11"
register "pirqe_routing" = "PCH_IRQ11"
register "pirqf_routing" = "PCH_IRQ11"
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
register "EnableSata" = "1"
register "SataSalpSupport" = "1"