soc/intel/apollolake: Fix parenthesis issues
Fix the following errors and warning detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: return is not a function, parentheses are not required WARNING: space prohibited between function name and open parenthesis '(' TEST=Build for reef Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18725 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -287,7 +287,7 @@ static void acpigen_soc_get_dw0_in_local5(uintptr_t addr)
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static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
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{
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assert (gpio_num < TOTAL_PADS);
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assert(gpio_num < TOTAL_PADS);
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uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
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acpigen_soc_get_dw0_in_local5(addr);
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@ -313,7 +313,7 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
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static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
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{
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assert (gpio_num < TOTAL_PADS);
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assert(gpio_num < TOTAL_PADS);
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uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
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acpigen_soc_get_dw0_in_local5(addr);
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@ -52,7 +52,7 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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return;
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/* Loaded program segment should lie entirely within CAR region. */
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assert (start_car_check && end_car_check);
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assert(start_car_check && end_car_check);
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flush_l1d_to_l2();
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}
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@ -49,7 +49,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* PME */
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if(ps->gpe0_sts[GPE0_A] & CSE_PME_STS)
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if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* SMBUS Wake */
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@ -143,7 +143,7 @@ static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
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/* Set enable bits */
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en_reg = GPI_SMI_EN_OFFSET(group);
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value = iosf_read(port, en_reg );
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value = iosf_read(port, en_reg);
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value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP);
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iosf_write(port, en_reg, value);
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}
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@ -348,7 +348,7 @@ int gpi_status_get(const struct gpi_status *sts, gpio_t gpi)
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/* Helper function to map PMC register groups to tier1 sci groups */
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static int pmc_gpe_route_to_gpio(int route)
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{
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switch(route) {
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switch (route) {
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case PMC_GPE_SW_31_0:
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return GPIO_GPE_SW_31_0;
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case PMC_GPE_SW_63_32:
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@ -61,7 +61,7 @@ void reset_prepare(void)
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void chipset_handle_reset(uint32_t status)
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{
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switch(status) {
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switch (status) {
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case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */
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global_reset();
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break;
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@ -65,7 +65,7 @@ void lpss_console_uart_init(void)
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uintptr_t uart_platform_base(int idx)
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{
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return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
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return CONFIG_CONSOLE_UART_BASE_ADDRESS;
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}
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static const struct pad_config uart_gpios[] = {
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