mb/hp/280_g2: Add new mainboard
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots. There are two possible BOM configurations: Sid has no legacy devices, whereas Manny provides two serial ports, a parallel port, a PCI slot and PS/2 keyboard/mouse connectors. These boards also have different Super I/O models: Manny uses an ITE IT8625E, whereas legacy-free Sid comes with an ITE IT8656E instead. This coreboot port has been done using a Sid board, thus support for Manny-specific features is missing. Booting should still be possible, though: none of these legacy features is essential. The board has an unpopulated 6-pin header, wired to PCH UART 2. This can be used to retrieve coreboot logs. Working: - Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH) - PCH SerialIO UART 2 to get coreboot logs - Rear USB ports - Realtek RTL8111 GbE NIC - Integrated graphics on DVI with libgfxinit - At least one SATA port - Flashing internally with flashrom - S3 suspend/resume - VBT - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1) Untested: - Audio - VGA: DP2VGA chip uses DDI E, and libgfxinit doesn't support DDI E yet - Front USB headers - Non-Linux OSes - PCI slot - IT8625E peripherals: serial, parallel and PS/2 ports Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48386 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
44948a7c5c
commit
d8fcd42089
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_HP_280_G2
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LIBGFXINIT
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select SKYLAKE_SOC_PCH_H
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_KABYLAKE
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select SPD_READ_BY_WORD
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select SUPERIO_ITE_COMMON_PRE_RAM
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config MAINBOARD_DIR
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string
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default "hp/280_g2"
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config MAINBOARD_PART_NUMBER
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string
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default "280 G2"
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config UART_FOR_CONSOLE
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int
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default 2
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config USE_LEGACY_8254_TIMER
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default y
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endif
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config BOARD_HP_280_G2
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bool "280 G2"
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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ramstage-y += hda_verb.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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Vendor name: HP
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Board name: 280 G2
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Category: desktop
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Board URL: https://support.hp.com/us-en/document/c04955444
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/pnp_ops.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <superio/ite/common/ite.h>
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#include <types.h>
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static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */
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PAD_CFG_NF(GPP_C20, UP_20K, PLTRST, NF1), /* PCH_UART2_RXD */
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PAD_CFG_NF(GPP_C21, UP_20K, PLTRST, NF1), /* PCH_UART2_TXD */
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PAD_NC(GPP_C22, NONE),
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PAD_CFG_GPI(GPP_C23, NONE, PLTRST), /* TODO: SIO PME# */
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* SATA_LED# */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC_LAN# */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB3.0_OC_BACK# */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC_REAR2# */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USB_OC_FRONT1# */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* USB_OC_FRONT2# */
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PAD_CFG_GPI(GPP_G1, NONE, PLTRST), /* LPT_DET# */
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PAD_CFG_GPO(GPP_G2, 0, PLTRST), /* AUD_AMP_ON# */
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PAD_CFG_GPO(GPP_G3, 0, PLTRST), /* W_DISABLE2# */
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PAD_CFG_GPI(GPP_G4, NONE, PLTRST), /* CLR_CMOS# */
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PAD_CFG_GPI(GPP_G5, NONE, PLTRST), /* CLR_PSWD# */
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PAD_CFG_GPI(GPP_G6, NONE, PLTRST), /* BOOT_BLOCK_EN# */
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PAD_CFG_GPI(GPP_G9, NONE, PLTRST), /* HOOD_SW_DET# */
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PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* FRONT_USB_DET1# */
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PAD_CFG_GPI(GPP_G13, NONE, PLTRST), /* FRONT_USB_DET2# */
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PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* FRONT_USB_DET3# */
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PAD_CFG_GPI(GPP_G16, NONE, PLTRST), /* F_AUDIO_DET# */
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PAD_CFG_GPI(GPP_G17, NONE, PLTRST), /* COMM_B_DET# */
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PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), /* SPI_TPM_PIRQ# */
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PAD_CFG_GPI(GPP_H10, NONE, PLTRST), /* S_GPI_SKU0 */
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PAD_CFG_GPI(GPP_H15, NONE, PLTRST), /* BRD_REV0 */
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PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* BRD_REV1 */
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PAD_CFG_GPI(GPP_H17, NONE, PLTRST), /* BRD_REV2 */
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PAD_CFG_GPI(GPP_H18, NONE, PLTRST), /* S_GPI_SKU1 */
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PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DPD_HPD_R */
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PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), /* DPE_HPD_R */
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PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */
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PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), /* DDPD_CTRLDATA */
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};
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static void mainboard_configure_super_io(void)
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{
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const pnp_devfn_t dev = PNP_DEV(0x2e, 7);
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_write_config(dev, 0x23, 0x59);
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pnp_write_config(dev, 0x25, 0x10);
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pnp_write_config(dev, 0x26, 0x04);
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pnp_write_config(dev, 0x28, 0x08);
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pnp_write_config(dev, 0x2a, 0x81);
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pnp_write_config(dev, 0x71, 0x08);
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pnp_write_config(dev, 0xc0, 0x00);
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pnp_write_config(dev, 0xc1, 0x04);
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pnp_write_config(dev, 0xc8, 0x00);
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pnp_write_config(dev, 0xc9, 0x04);
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pnp_write_config(dev, 0xcb, 0x08);
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pnp_write_config(dev, 0xd5, 0x07);
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pnp_write_config(dev, 0xf8, 0x12);
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pnp_write_config(dev, 0xf9, 0x01);
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pnp_exit_conf_state(dev);
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}
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void bootblock_mainboard_early_init(void)
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{
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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mainboard_configure_super_io();
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}
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void bootblock_mainboard_init(void)
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{
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const gpio_t rev_gpios[] = {
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GPP_H15,
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GPP_H16,
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GPP_H17,
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};
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const char *const rev_table[8] = {
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[0] = "DB",
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[1] = "Pre-SI",
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[2] = "SI",
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[3] = "PV",
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[4] = "1.00 (SMVB)",
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[5] = "1.10 (ECN1)",
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[6] = "1.20 (ECN1)",
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[7] = "1.30 (ECN1)",
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};
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const char *const brd_str = gpio_get(GPP_H10) ? "Sid" : "Manny";
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const uint32_t brd_rev = gpio_base2_value(rev_gpios, ARRAY_SIZE(rev_gpios));
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printk(BIOS_DEBUG, "Mainboard: %s rev %s\n", brd_str, rev_table[brd_rev]);
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}
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Binary file not shown.
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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/skylake
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */
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}"
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register "eist_enable" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x103c 0x2b5e inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe graphics
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device pci 02.0 on end # iGPU
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device pci 04.0 on end # CPU Thermal
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device pci 08.0 on end # GMM
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device pci 14.0 on # xHCI
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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end
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device pci 14.1 off end # USB OTG
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device pci 14.2 on end # PCH Thermal
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # MEI #1
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device pci 16.1 off end # MEI #2
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device pci 16.2 off end # ME IDE-R
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device pci 16.3 off end # ME KT
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device pci 16.4 off end # MEI #3
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device pci 17.0 on # SATA
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register "SataMode" = "SATA_AHCI"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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register "SataPortsHotPlug" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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# DevSlp not supported
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# Enable test mode for SATA margining
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register "SataTestMode" = "1"
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end
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device pci 19.0 on end # UART #2
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device pci 1c.0 off end # RP #1
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device pci 1c.1 off end # RP #2
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device pci 1c.2 off end # RP #3
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device pci 1c.3 off end # RP #4
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device pci 1c.4 on # RP #5: IT8893E PCI Bridge
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpClkSrcNumber[4]" = "11"
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end
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device pci 1c.5 on # RP #6: PCIe x1 slot
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register "PcieRpEnable[5]" = "1"
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register "PcieRpHotPlug[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpClkSrcNumber[5]" = "6"
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end
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device pci 1c.6 on # RP #7: RTL8111 GbE NIC
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieRpAdvancedErrorReporting[6]" = "1"
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register "PcieRpClkSrcNumber[6]" = "10"
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end
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device pci 1c.7 on # RP #8: M.2 2230 slot
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register "PcieRpEnable[7]" = "1"
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register "PcieRpHotPlug[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieRpAdvancedErrorReporting[7]" = "1"
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register "PcieRpClkSrcNumber[7]" = "12"
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end
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device pci 1d.0 off end # RP #9
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device pci 1d.1 off end # RP #10
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device pci 1d.2 off end # RP #11
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device pci 1d.3 off end # RP #12
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC bridge
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# FIXME: Missing Super I/O HWM config
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register "gen1_dec" = "0x000c0291"
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on # PMC
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register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
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register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
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register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
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register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
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register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
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end
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI
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device pci 1f.6 off end # Intel GbE
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device pci 1f.7 on # Trace Hub
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register "TraceHubMemReg0Size" = "2"
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register "TraceHubMemReg1Size" = "2"
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end
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(HDMI3, -- DVI-I
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eDP, -- VGA
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others => Disabled);
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end GMA.Mainboard;
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* coreboot specific header */
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0x10ec0221, /* Codec Vendor / Device ID: Realtek ALC221 */
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0x103c2b5e, /* Subsystem ID */
|
||||
11, /* Number of jacks */
|
||||
AZALIA_SUBVENDOR(0, 0x103c2b5e),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x90170120),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x01813030),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4044c301),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x0221101f),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <fsp/soc_binding.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <spd_bin.h>
|
||||
#include <string.h>
|
||||
#include <types.h>
|
||||
|
||||
/* Rcomp resistors are located on the CPU package */
|
||||
static const u16 rcomp_resistors[3] = { 121, 75, 100 };
|
||||
|
||||
/* Rcomp targets for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk */
|
||||
static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 };
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig;
|
||||
|
||||
struct spd_block blk = {
|
||||
.addr_map = { 0x51, 0x50 },
|
||||
};
|
||||
|
||||
get_spd_smbus(&blk);
|
||||
|
||||
mem_cfg->DqPinsInterleaved = true;
|
||||
|
||||
mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
|
||||
|
||||
mem_cfg->MemorySpdDataLen = blk.len;
|
||||
mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
|
||||
mem_cfg->MemorySpdPtr10 = (u32)blk.spd_array[1];
|
||||
|
||||
assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
|
||||
assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));
|
||||
|
||||
memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor));
|
||||
memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget));
|
||||
|
||||
/* These settings are most likely useless if using a release build of FSP */
|
||||
mem_cfg->PcdDebugInterfaceFlags = 2; /* Enable UART */
|
||||
mem_cfg->PcdSerialIoUartNumber = 2; /* Use UART #2 */
|
||||
mem_cfg->PcdSerialDebugBaudRate = 7; /* 115200 baud */
|
||||
mem_cfg->PcdSerialDebugLevel = 3; /* Log <= Info */
|
||||
|
||||
/* Trace Hub */
|
||||
mem_cfg->PcdDebugInterfaceFlags |= 1 << 5;
|
||||
|
||||
/* Allow changing memory timings after MRC is done */
|
||||
mem_cfg->RealtimeMemoryTiming = 1;
|
||||
mem_cfg->SaOcSupport = 1;
|
||||
}
|
||||
Loading…
Reference in New Issue