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amd/cimx: fix sb(8|9)00 NULL type redefine 

It is inappropriate for chipset code to be redefining
types -- especially NULL to a non-pointer type. There's
only one non-straight forward change. A condition
being checked was '!ptr_type == NULL' (0 as int). That
check is actually 'ptr_type != NULL'.

Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5088
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Aaron Durbin 2014-01-30 22:20:01 -06:00 committed by Aaron Durbin
parent 6ecdb68562
commit d907a3402e
14 changed files with 28 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/southbridge/amd/cimx/sb800/SBPLATFORM.h
View File

@ -24,11 +24,7 @@
#ifndef _AMD_SBPLATFORM_H_
#define _AMD_SBPLATFORM_H_
//#include "cbtypes.h"
#ifdef NULL
#undef NULL
#endif
#define NULL 0
#include <stddef.h>
typedef unsigned long long PLACEHOLDER;

6
src/southbridge/amd/cimx/sb900/SbPlatform.h
View File

@ -24,11 +24,7 @@
#ifndef _AMD_SBPLATFORM_H_
#define _AMD_SBPLATFORM_H_
//#include "cbtypes.h"
#ifdef NULL
#undef NULL
#endif
#define NULL 0
#include <stddef.h>
typedef unsigned long long PLACEHOLDER;

6
src/southbridge/amd/cimx/sb900/cfg.c
View File

@ -178,7 +178,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
// sb_config->HpetMsiDis = 0; // Field Retired
// sb_config->ResetCpuOnSyncFlood = 0; // Field Retired
// sb_config->PcibAutoClkCtr = 0; // Field Retired
sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level
sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level
sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used
sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used
@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option
sb_config->sdbEnable = 0; // CIMx Internal Used
sb_config->TempMMIO = NULL; // CIMx Internal Used
sb_config->TempMMIO = (typeof(sb_config->TempMMIO))NULL; // CIMx Internal Used
// sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired
sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option
sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option
@ -296,7 +296,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config)
sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option
sb_config->NbSbGen2 = NB_SB_GEN2; // External Option
sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option
sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level
sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level
sb_config->sdbEnable = 0; // CIMx Internal Used
sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option

2
src/vendorcode/amd/cimx/sb800/AZALIA.c
View File

@ -284,7 +284,7 @@ azaliaInitAfterPciEnum (
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);

2
src/vendorcode/amd/cimx/sb800/GEC.c
View File

@ -113,7 +113,7 @@ gecInitAfterPciEnum (
ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);
dbTemp = 0x07;
WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);
if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);

14
src/vendorcode/amd/cimx/sb800/SATA.c
View File

@ -258,7 +258,7 @@ sataInitBeforePciEnum (
UINT16 i;
SATAPHYSETTING *pPhyTable;
ddTempVar = NULL;
ddTempVar = 0;
// BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
// BIT4: Disable fast boot
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);
@ -292,17 +292,17 @@ sataInitBeforePciEnum (
//Set PATA controller to native mode
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
}
if (pConfig->BuildParameters.IdeSsid != NULL ) {
if (pConfig->BuildParameters.IdeSsid != 0 ) {
RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
}
// SATA Controller Class ID & SSID
pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
if ( pConfig->BuildParameters.SataIDESsid != NULL ) {
if ( pConfig->BuildParameters.SataIDESsid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataIDESsid;
}
dwDeviceId = pDeviceIdptr[dbValue];
if ( pConfig->SataClass == RAID_MODE) {
if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) {
if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
}
dwDeviceId = V_SB_SATA_RAID5_DID;
@ -310,19 +310,19 @@ sataInitBeforePciEnum (
getEfuseStatus (&pValue);
if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
dwDeviceId = V_SB_SATA_RAID_DID;
if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) {
if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
}
}
}
if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {
if ( pConfig->BuildParameters.SataAHCISsid != 0 ) {
ddTempVar = pConfig->BuildParameters.SataAHCISsid;
}
}
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
if ( ddTempVar != NULL ) {
if ( ddTempVar != 0 ) {
RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
}
// SATA IRQ Resource

4
src/vendorcode/amd/cimx/sb800/SBCMN.c
View File

@ -378,7 +378,7 @@ commonInitEarlyBoot (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
//Early post initialization of pci config space
programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
}
//Make BAR registers of smbus invisible.
@ -388,7 +388,7 @@ commonInitEarlyBoot (
// LPC CFG programming
//
// SSID for LPC Controller
if (pConfig->BuildParameters.LpcSsid != NULL ) {
if (pConfig->BuildParameters.LpcSsid != 0 ) {
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
}
// LPC MSI

2
src/vendorcode/amd/cimx/sb800/SBPOR.c
View File

@ -150,7 +150,7 @@ sbPowerOnInit (
cimNbSbGen2 = pConfig->NbSbGen2;
cimSataMode = pConfig->SATAMODE.SataModeReg;
// Adding Fast Read Function support
if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
} else {
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;

6
src/vendorcode/amd/cimx/sb800/USB.c
View File

@ -196,7 +196,7 @@ EhciInitAfterPciInit (
if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
if (pConfig->BuildParameters.EhciSsid != NULL ) {
if (pConfig->BuildParameters.EhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
}
//USB Common PHY CAL & Control Register setting
@ -308,7 +308,7 @@ usb4OhciInitAfterPciInit (
UINT32 ddDeviceId;
ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
}
}
@ -327,7 +327,7 @@ OhciInitAfterPciInit (
// SB02186
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
if ( pConfig->BuildParameters.OhciSsid != NULL ) {
if ( pConfig->BuildParameters.OhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
}
}

2
src/vendorcode/amd/cimx/sb900/Azalia.c
View File

@ -282,7 +282,7 @@ azaliaInitAfterPciEnum (
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);

2
src/vendorcode/amd/cimx/sb900/Gec.c
View File

@ -109,7 +109,7 @@ gecInitAfterPciEnum (
VOID* GecRomAddress;
VOID* GecShadowRomAddress;
UINT32 ddTemp;
if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);

2
src/vendorcode/amd/cimx/sb900/Sata.c
View File

@ -458,7 +458,7 @@ sataInitBeforePciEnum (
//Set PATA controller to native mode
RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
}
if (pConfig->BuildParameters.IdeSsid != NULL ) {
if (pConfig->BuildParameters.IdeSsid != 0 ) {
RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
}
// SATA Controller Class ID & SSID

4
src/vendorcode/amd/cimx/sb900/SbCmn.c
View File

@ -398,7 +398,7 @@ commonInitEarlyBoot (
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
//Early post initialization of pci config space
programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
}
//Make BAR registers of smbus invisible.
@ -408,7 +408,7 @@ commonInitEarlyBoot (
// LPC CFG programming
//
// SSID for LPC Controller
if (pConfig->BuildParameters.LpcSsid != NULL ) {
if (pConfig->BuildParameters.LpcSsid != 0 ) {
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
}
// LPC MSI

6
src/vendorcode/amd/cimx/sb900/Usb.c
View File

@ -357,7 +357,7 @@ EhciInitAfterPciInit (
if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
if (pConfig->BuildParameters.EhciSsid != NULL ) {
if (pConfig->BuildParameters.EhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
}
//USB Common PHY CAL & Control Register setting
@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit (
UINT32 ddDeviceId;
ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
}
}
@ -595,7 +595,7 @@ OhciInitAfterPciInit (
// RPR USB SMI Handshake
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
if ( pConfig->BuildParameters.OhciSsid != NULL ) {
if ( pConfig->BuildParameters.OhciSsid != 0 ) {
RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
}
}