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mb/google/kohaku: Adjust I2C clock frequency 

All serial I2C bus frequencies should not be over 400KHz in kohaku,
but the measurement showed frequencies of I2C1 and I2C4 were over
400KHz. (b:144885961)

This change adjusts I2C speed settings to limit that frequencies to
400KHz.

The new setting values have been from other projects using same I2C
components, and verified I2C1 and I2C4 frequencies < 400MHz internally.

BUG=b:144885961
BRANCH=firmware-hatch-12672.B
TEST=Verified I2C1 and I2C4 frequency not over 400KHz

Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Seunghwan Kim 2019-11-28 16:35:02 +09:00 committed by Patrick Georgi
parent 2f35744e40
commit d9105d98b7
1 changed files with 4 additions and 2 deletions
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6
src/mainboard/google/hatch/variants/kohaku/overridetree.cb
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@ -60,6 +60,8 @@ chip soc/intel/cannonlake
}, },
.i2c[1] = { .i2c[1] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 60,
.fall_time_ns = 25,
}, },
.i2c[2] = { .i2c[2] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
@ -68,8 +70,8 @@ chip soc/intel/cannonlake
}, },
.i2c[4] = { .i2c[4] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.rise_time_ns = 100, .rise_time_ns = 104,
.fall_time_ns = 20, .fall_time_ns = 52,
}, },
.gspi[0] = { .gspi[0] = {
.speed_mhz = 1, .speed_mhz = 1,